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 CX81801-7x/8x SmartV.XX Modem Data Sheet
Contents
1. Introduction..........................................................................................................................................1-1
1.1 1.2 1.3 Overview ......................................................................................................................................................................... 1-1 Applications .................................................................................................................................................................... 1-2 Features .......................................................................................................................................................................... 1-4 1.3.1 General Modem Features................................................................................................................................ 1-4 1.3.2 SmartDAA Features ........................................................................................................................................ 1-5 1.3.3 Applications.................................................................................................................................................... 1-5 Technical Overview......................................................................................................................................................... 1-6 1.4.1 General Description ........................................................................................................................................ 1-6 1.4.2 MCU Firmware................................................................................................................................................ 1-6 1.4.3 Operating Modes ............................................................................................................................................ 1-6 1.4.3.1 Data/Fax Modes.......................................................................................................................... 1-6 1.4.3.2 V.44 Data Compression.............................................................................................................. 1-7 1.4.3.3 Worldwide Operation.................................................................................................................. 1-7 1.4.3.4 TAM Mode.................................................................................................................................. 1-8 1.4.3.5 Speakerphone Mode (S Models)................................................................................................ 1-9 1.4.4 Reference Designs.......................................................................................................................................... 1-9 Hardware Description ..................................................................................................................................................... 1-9 1.5.1 CX81801 Modem Device ................................................................................................................................ 1-9 1.5.2 Digital Isolation Barrier................................................................................................................................. 1-10 1.5.3 CX20493 SmartDAA Line Side Device.......................................................................................................... 1-10 1.5.4 CX20442 Voice Codec .................................................................................................................................. 1-10 AT Commands .............................................................................................................................................................. 1-10 Serial DTE Interface Operation........................................................................................................................................ 2-1 2.1.1 Automatic Speed/Format Sensing .................................................................................................................. 2-1 Parallel Host Bus Interface Operation............................................................................................................................. 2-2 Establishing Data Modem Connections .......................................................................................................................... 2-2 2.3.1 Dialing ............................................................................................................................................................ 2-2 2.3.2 Telephone Number Directory.......................................................................................................................... 2-2 2.3.3 Modem Handshaking Protocol ....................................................................................................................... 2-2 2.3.4 Call Progress Tone Detection ......................................................................................................................... 2-2 2.3.5 Answer Tone Detection................................................................................................................................... 2-2 2.3.6 Ring Detection................................................................................................................................................ 2-2 2.3.7 Billing Protection ............................................................................................................................................ 2-3 2.3.8 Connection Speeds......................................................................................................................................... 2-3 2.3.9 Automode ....................................................................................................................................................... 2-3 Data Mode ...................................................................................................................................................................... 2-4
1.4
1.5
1.6 2.1 2.2 2.3
2. Technical Specifications .......................................................................................................................2-1
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2.4.1 Speed Buffering (Normal Mode) .................................................................................................................... 2-4 2.4.2 Flow Control ................................................................................................................................................... 2-4 2.4.3 Escape Sequence Detection............................................................................................................................ 2-4 2.4.4 BREAK Detection ............................................................................................................................................ 2-4 2.4.5 Telephone Line Monitoring............................................................................................................................. 2-4 2.4.6 Fall Forward/Fallback (V.92/V.90/V.34/V.32 bis/V.32) ................................................................................... 2-4 2.4.7 Retrain ............................................................................................................................................................ 2-5 2.4.8 Programmable Inactivity Timer ...................................................................................................................... 2-5 2.4.9 DTE Signal Monitoring (Serial DTE Interface Only) ........................................................................................ 2-5 V.92 Features.................................................................................................................................................................. 2-5 2.5.1 Modem-on-Hold ............................................................................................................................................. 2-5 2.5.2 Quick Connect ................................................................................................................................................ 2-6 2.5.3 PCM Upstream ............................................................................................................................................... 2-6 Error Correction and Data Compression......................................................................................................................... 2-6 2.6.1 V.42 Error Correction ..................................................................................................................................... 2-6 2.6.2 MNP 2-4 Error Correction .............................................................................................................................. 2-6 2.6.3 V.44 Data Compression.................................................................................................................................. 2-6 2.6.4 V.42 bis Data Compression ............................................................................................................................ 2-6 2.6.5 MNP 5 Data Compression .............................................................................................................................. 2-7 Telephony Extensions..................................................................................................................................................... 2-7 2.7.1 Line In Use Detection ..................................................................................................................................... 2-7 2.7.2 Extension Pickup Detection ............................................................................................................................ 2-7 2.7.3 Remote Hangup Detection.............................................................................................................................. 2-8 Fax Class 1 and Fax Class 1.0 Operation ........................................................................................................................ 2-8 Point-of-Sales Support ................................................................................................................................................... 2-8 Voice/Audio Mode .......................................................................................................................................................... 2-8 2.10.1 Online Voice Command Mode ........................................................................................................................ 2-8 2.10.2 Voice Receive Mode ....................................................................................................................................... 2-8 2.10.3 Voice Transmit Mode ..................................................................................................................................... 2-9 2.10.4 Full-Duplex Receive and Transmit Mode ........................................................................................................ 2-9 2.10.5 Audio Mode .................................................................................................................................................... 2-9 2.10.6 Tone Detectors ............................................................................................................................................... 2-9 2.10.7 Speakerphone Mode....................................................................................................................................... 2-9 V.80 Synchronous Access Mode (SAM) - Video Conferencing ...................................................................................... 2-9 Full-Duplex Speakerphone (FDSP) Mode (S Models)................................................................................................... 2-10 Caller ID ........................................................................................................................................................................ 2-10 Worldwide Country Support ......................................................................................................................................... 2-10 Diagnostics ................................................................................................................................................................... 2-11 2.15.1 Commanded Tests........................................................................................................................................ 2-11 2.15.2 Power On Reset Tests .................................................................................................................................. 2-11 Low Power Sleep Mode ................................................................................................................................................ 2-12 CX81801 Modem Hardware Pins and Signals ................................................................................................................ 3-1 3.1.1 Common to Parallel and Serial Interface Configurations................................................................................ 3-1 3.1.1.1 LSD Interface (Through DIB)...................................................................................................... 3-1 3.1.1.2 Call Progress Speaker Interface ................................................................................................. 3-1 3.1.1.3 Voice Relay Interface (S Models) ............................................................................................... 3-1 3.1.1.4 Serial EEPROM Interface............................................................................................................ 3-1 3.1.1.5 External Bus Interface ................................................................................................................ 3-2
2.5
2.6
2.7
2.8 2.9 2.10
2.11 2.12 2.13 2.14 2.15
2.16 3.1
3. Hardware Interface ...............................................................................................................................3-1
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3.1.2 Serial Interface Configuration Only................................................................................................................. 3-2 3.1.2.1 Serial DTE Interface and Indicator Outputs (PARIF = Low)........................................................ 3-2 3.1.3 Parallel Interface Configuration Only (PARIF = High)..................................................................................... 3-3 3.1.3.1 Parallel Host Bus Interface ......................................................................................................... 3-3 3.1.4 CX81801 Modem Interface Signals................................................................................................................ 3-3 CX20493 LSD Hardware Pins and Signals ................................................................................................................... 3-22 3.2.1 CX20493 LSD Signal Summary.................................................................................................................... 3-22 3.2.1.1 Smart Modem Interface (Through DIB) ................................................................................... 3-22 3.2.1.2 Telephone Line Interface .......................................................................................................... 3-22 3.2.1.3 Voltage References................................................................................................................... 3-22 3.2.1.4 General Purpose Input/Output.................................................................................................. 3-23 3.2.1.5 No Connects ............................................................................................................................. 3-23 3.2.2 CX20493 LSD Pin Assignments and Signal Definitions ............................................................................... 3-23 CX20442 VC Hardware Pins and Signals (S Models)................................................................................................... 3-28 3.3.1 CX20442 VC Signal Summary...................................................................................................................... 3-28 3.3.1.1 Speakerphone Interface............................................................................................................ 3-28 3.3.1.2 Telephone Handset/Headset Interface...................................................................................... 3-28 3.3.1.3 CX81801 Modem Interface....................................................................................................... 3-28 3.3.1.4 Host Interface........................................................................................................................... 3-28 3.3.2 CX20442 VC Pin Assignments and Signal Definitions ................................................................................. 3-29 Electrical and Environmental Specifications ................................................................................................................. 3-35 3.4.1 Operating Conditions, Absolute Maximum Ratings, and Power Requirements ........................................... 3-35 3.4.2 Interface and Timing Waveforms ................................................................................................................. 3-37 3.4.2.1 External Memory Bus Timing ................................................................................................... 3-37 3.4.2.2 Parallel Host Bus Timing .......................................................................................................... 3-39 3.4.2.3 Serial DTE Interface.................................................................................................................. 3-41 Crystal Specifications ................................................................................................................................................... 3-42
3.2
3.3
3.4
3.5
4. Package Dimensions ............................................................................................................................4-1 5. Parallel Host Interface ..........................................................................................................................5-1
5.1 5.2 Overview ......................................................................................................................................................................... 5-1 Register Signal Definitions ............................................................................................................................................. 5-3 5.2.1 IER - Interrupt Enable Register (Addr = 1, DLAB = 0) .................................................................................... 5-3 5.2.2 FCR - FIFO Control Register (Addr = 2, Write Only) ....................................................................................... 5-4 5.2.3 IIR - Interrupt Identifier Register (Addr = 2) .................................................................................................. 5-5 5.2.4 LCR - Line Control Register (Addr = 3) .......................................................................................................... 5-6 5.2.5 MCR - Modem Control Register (Addr = 4).................................................................................................... 5-7 5.2.6 LSR - Line Status Register (Addr = 5)............................................................................................................ 5-7 5.2.7 MSR - Modem Status Register (Addr = 6) ..................................................................................................... 5-9 5.2.8 RBR - RX Buffer (Receiver Buffer Register) (Addr = 0, DLAB = 0) ................................................................ 5-9 5.2.9 THR - TX Buffer (Transmitter Holding Register) (Addr = 0, DLAB = 0).......................................................... 5-9 5.2.10 Divisor Registers (Addr = 0 and 1, DLAB = 1).............................................................................................. 5-10 Receiver FIFO Interrupt Operation ................................................................................................................................ 5-10 5.3.1 Receiver Data Available Interrupt ................................................................................................................. 5-10 5.3.2 Receiver Character Timeout Interrupts......................................................................................................... 5-11 Transmitter FIFO Interrupt Operation ........................................................................................................................... 5-11 5.4.1 Transmitter Empty Interrupt......................................................................................................................... 5-11
5.3
5.4
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Figures
Figure 1-1. SmartV.XX Modem Simplified Interface Diagram ............................................................................................ 1-3 Figure 1-2. SmartV.XX Modem Major Interfaces................................................................................................................ 1-3 Figure 2-1. TMIND# Test Results Pulse Cycles ................................................................................................................ 2-12 Figure 3-1. CX81801 Modem Hardware Signals for Parallel Interface (PARIF = High) ...................................................... 3-4 Figure 3-2. CX81801 Modem 128-Pin TQFP Pin Signals for Parallel Interface (PARIF = High) ......................................... 3-5 Figure 3-3. CX81801 Modem Hardware Signals for Serial Interface (PARIF = Low)........................................................ 3-12 Figure 3-4. CX81801 Modem 128-Pin TQFP Pin Signals for Serial Interface (PARIF = Low)........................................... 3-13 Figure 3-5. CX20493 LSD Hardware Interface Signals ..................................................................................................... 3-23 Figure 3-6. CX20493 LSD 28-Pin QFN Pin Signals........................................................................................................... 3-24 Figure 3-7. CX20442 VC Hardware Interface Signals ....................................................................................................... 3-30 Figure 3-8. CX20442 VC 32-Pin TQFP Pin Signals ........................................................................................................... 3-30 Figure 3-9. Waveforms - External Memory Bus................................................................................................................ 3-38 Figure 3-10. Waveforms - Parallel Host Bus..................................................................................................................... 3-40 Figure 3-11. Waveforms - Serial DTE Interface ................................................................................................................ 3-41 Figure 4-1. Package Dimensions - 128-Pin TQFP............................................................................................................... 4-2 Figure 4-2. Package Dimensions - 32-pin TQFP ................................................................................................................. 4-3 Figure 4-3. Package Dimensions - 28-Pin QFN................................................................................................................... 4-4
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Tables
Table 1-1. SmartV.XX Modem Models and Functions ........................................................................................................ 1-2 Table 1-2. Default Countries Supported.............................................................................................................................. 1-8 Table 2-1. +MS Command Automode Connectivity ............................................................................................................ 2-3 Table 3-1. CX81801 Modem 128-Pin TQFP Pin Signals for Parallel Interface (PARIF = High)........................................... 3-6 Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High) ................................................. 3-8 Table 3-3. CX81801 Modem 128-Pin TQFP Pin Signals for Serial Interface (PARIF = Low) ............................................ 3-14 Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low)................................................... 3-16 Table 3-5. CX81801 Modem I/O Type Definitions ............................................................................................................ 3-21 Table 3-6. CX81801 Modem DC Electrical Characteristics ............................................................................................... 3-21 Table 3-7. CX20493 LSD 28-Pin QFN Pin Signals ............................................................................................................ 3-24 Table 3-8. CX20493 LSD Hardware Signal Definitions ..................................................................................................... 3-25 Table 3-9. CX20493 LSD GPIO DC Electrical Characteristics ........................................................................................... 3-27 Table 3-10. CX20493 AVdd DC Electrical Characteristics................................................................................................. 3-27 Table 3-11. CX20442 VC 32-Pin TQFP Pin Signals........................................................................................................... 3-31 Table 3-12. CX20442 VC Pin Signal Definitions ............................................................................................................... 3-32 Table 3-13. CX20442 VC DC Electrical Characteristics..................................................................................................... 3-33 Table 3-14. CX20442 VC Analog Electrical Characteristics............................................................................................... 3-34 Table 3-15. Operating Conditions ..................................................................................................................................... 3-35 Table 3-16. CX81801 Absolute Maximum Ratings ........................................................................................................... 3-35 Table 3-17. CX20493 Absolute Maximum Ratings ........................................................................................................... 3-35 Table 3-18. CX20442 Absolute Maximum Ratings ........................................................................................................... 3-36 Table 3-19. Current and Power Requirements.................................................................................................................. 3-36 Table 3-20. Timing - External Memory Bus ...................................................................................................................... 3-37 Table 3-21. Timing - Parallel Host Bus ............................................................................................................................. 3-39 Table 3-22. Crystal Specifications..................................................................................................................................... 3-42 Table 5-1. Parallel Interface Registers ................................................................................................................................ 5-2 Table 5-2. Interrupt Sources and Reset Control ................................................................................................................. 5-5 Table 5-3. Programmable Baud Rates .............................................................................................................................. 5-10
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1.
1.1
Introduction
Overview
The Conexant(R) SmartV.XX Modem is a full-featured, worldwide, controller-based modem that integrates modem controller (MCU), modem data pump (MDP), 256 KB ROM, 32 KB RAM, and SmartDAA system side device (SSD) functions onto a single die. The modem operates by executing firmware from internal ROM and RAM. Optional customized firmware is supported with optional external flash ROM memory. Additionally, added/modified country profiles are supported by internal SRAM patch (maximum of one profile) or serial EEPROM. Downloadable architecture supports downloading of customized MCU firmware from the host/DTE to the SmartV.XX modem. The SmartV.XX Modem device set consists of a CX81801 modem device in a 128-pin TQFP and a CX20493 SmartDAA Line Side Device (LSD) in a 28-pin QFN. Conexant's SmartDAA(R) technology eliminates the need for a costly analog transformer, relays and opto-isolations typically used in discrete DAA (Data Access Arrangement) implementations. The SmartDAA architecture also simplifies product implementation by eliminating the need for country-specific board configurations enabling worldwide homologation of a single modem board design and a single bill of materials (BOM). Low profile, small TQFP and QFN packages with reduced voltage operation and low power consumption makes this device set an ideal solution for embedded and palmtop application using parallel host or serial DTE interface. The SmartV.XX Modem supports data rates up to V.92, data compression, error correction, fax rates up to 14.4 kbps and speakerphone mode. In V.92 and V.90 (V.92 models) data modes, the modem can receive data at speeds up to 56 kbps. In V.34 data mode (V.92 and V.34 models), the modem can receive data at speeds up to 33.6 kbps. In V.32 bis data mode, the modem can receive data at speeds up to 14.4 kbps. Data compress (V.44/V.42bis/MNP5) and error correction (V.42/MNP 2-4) modes are supported to maximize data throughput and data transfer integrity. Non-error-correction mode is also supported. Fax Group 3 send and receive rates are supported up to 14.4 kbps with T.30 protocol. The SmartV.XX modem operates with PSTN telephone lines worldwide. S models, using the optional CX20442 Voice Codec (VC) in a 32-pin TQFP, support position independent, full-duplex speakerphone (FDSP) operation using microphone and speaker, as well as other voice/TAM applications using handset or headset. Table 1-1 lists the available models. A simplified device interface drawing is shown in Figure 1-1. A functional interface drawing showing optional memory is shown in Figure 1-2.
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1.2
Applications
* * * * * * Set top boxes Gaming devices Point of sale terminals Remote monitoring and data collections systems Handheld computers Other embedded systems
Table 1-1. SmartV.XX Modem Models and Functions
Model/Order/Part Numbers Marketing Name Device Set Order No. Modem Device [128-Pin TQFP] Part No. Line Side Device (LSD) [28-Pin QFN] Part No. CX20493-21 CX20493-21 CX20493-31 CX20493-21 CX20493-21 CX20493-31 CX20493-21 CX20493-21 CX20493-31 Voice Codec (VC) [32-Pin TQFP] Part No. -- CX20442-11 -- -- CX20442-11 -- -- CX20442-11 -- V.90 Data, QC, MOH Supported Functions V.34 Data V.32 bis Data, V.44 Data Compression, V.17 Fax, TAM, Worldwide Y Y Y Y Y Y Y Y Y Voice/ FDSP
SmartV.92 SmartV.92/S SmartV.92/LF SmartV.34 SmartV.34/S SmartV.34/LF SmartV.32bis SmartV.32bis/S SmartV.32bis/LF Notes:
DS56-L147-203 DS56-L147-204 DS56-L147-206 DS28-L147-203 DS28-L147-204 DS28-L147-206 DS96-L147-203 DS96-L147-204 DS96-L147-206
CX81801-74 CX81801-74 CX81801-84 CX81801-72 CX81801-72 CX81801-82 CX81801-73 CX81801-73 CX81801-83
Y Y Y -- -- -- -- -- --
Y Y Y Y Y Y -- -- --
-- Y -- -- Y -- -- Y --
1. Supported functions (Y = Supported; -- = Not supported). QC, MOH, PCM Quick connect, Modem-on-Hold, PCM upstream TAM Telephone answering machine (Voice playback and record through telephone line) FDSP Full-duplex speakerphone and voice playback and record through telephone line, handset, and mic/speaker 2. For ordering purposes, the CX prefix may not be included in the part number for some devices. Also, the CX prefix may not appear in the part number as branded on some devices. 3. LF = Lead-free (Pb-free) devices.
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Figure 1-1. SmartV.XX Modem Simplified Interface Diagram
PARALLEL HOST BUS OR SERIAL DTE INTERFACE
Digital Isolation Barrier (DIB) CX81801 Modem 128-Pin TQFP
CX20493 SmartDAA Line Side Device (LSD) 28-Pin QFN
Telephone Line Interface Discrete Components
TIP RING TIP RING
TELEPHONE LINE HANDSET (OPTIONAL)
CX20442 Voice Codec (VC) 32-Pin TQFP (Optional)
MIC SPEAKER
(OPTIONAL)
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Figure 1-2. SmartV.XX Modem Major Interfaces
DAA Hardware CX81801 Modem 128-Pin TQFP CX20493 SmartDAA Line Side Device (LSD) 28-Pin QFN Digital Isolation Barrier (DIB) Components
Rectifier and Filter Components
SmartDAA Interface
Line Side DIB Interface (LSDI)
Codec
Telephone Line Interface
Telephone Line Interface Discrete Components
TELEPHONE LINE TIP RING
Voice Relay, HS Pickup Detector (Optional)
TELEPHONE HANDSET TIP RING
Paralle Host or Serial DTE Interface
Microcontroller Unit (MCU)
Modem Data Pump (MDP)
CX20442 Voice Codec (VC) 32-Pin TQFP (Optional)
HS Hybrid Components (Optional) (Mic/Speaker) Interface (Optional) MIC SPEAKER
Digital Speaker Circuit (Optional) RAM (32K x 8) Serial EEPROM 2K (256 x 8) to 256K (32K x 8) (Optional)
SOUNDUCER
ROM (256k x 8)
Optional RAM Up to 1M (128K x 8)
Optional Flash ROM Up to 4M (512K x 8)
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1.3
1.3.1
Features
General Modem Features
* Data modem - Quick connect, Modem-on-Hold, and PCM upstream functions (V.92 models) - ITU-T V.92/V.90 (V.92 models), V.34 (V.92 and V.34 models), V.32bis, V.32, V.29, FastPOS (V.29), V.22 bis, V.22, V.22 Fast Connect, V.23, V.21, Bell 212A, and Bell 103 - V.250 and V.251 commands Data compression and error correction - V.44 data compression - V.42 bis and MNP 5 data compression - V.42 LAPM and MNP 2-4 error correction Fax modem send and receive rates up to 14.4 kbps - V.17, V.29, V.27 ter, and V.21 channel 2 - EIA/TIA 578 Class 1 and T.31 Class 1.0 V.80 synchronous access mode supports host-controlled communication protocols with H.324 interface support Interfaces to optional external ROM/flash ROM, RAM, and/or optional serial EEPROM Data/Fax/Voice call discrimination Hardware-based modem controller Hardware-based digital signal processor (DSP) Worldwide operation - Complies to TBR21 and other country requirements - On-hook and/or off-hook Caller ID detection for selected countries - Call progress, blacklisting - Internal ROM includes default values for 29 countries - Additional and modified country profile can be stored in internal SRAM Caller waiting detection Caller ID detect - On-hook Caller ID detection - Off-hook Call Waiting Caller ID detection during data mode in V.92, V.90, V.34, V.32bis, and V.32 Distinctive ring detect Modem customization available through patch code that can be stored in optional serial EEPROM or internal SRAM Telephony/TAM - V.253 commands - 2-bit and 4-bit Conexant ADPCM, 8-bit linear PCM, and 4-bit IMA coding - 8 kHz sample rate - Concurrent DTMF, ring, and Caller ID detection
*
*
* * * * * *
* *
* * *
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*
* * * * * *
* *
Full-duplex speakerphone (FDSP) mode using optional CX20442 Voice Codec (S models) - Microphone and speaker interface - Telephone handset or headset interface - Acoustic and line echo cancellation - Microphone gain and muting - Speaker volume control and muting Built-in host/DTE interface - Parallel 16550A UART-compatible interface up to 230.4 kbps - Serial ITU-T V.24 (EIA/TIA-232-E) logical interface up to 115.2 kbps Downloadable architecture Direct mode (serial DTE interface) Flow control and speed buffering Automatic format/speed sensing Serial async/sync data; parallel async data Thin packages support low profile designs (1.6 mm max. height) - CX81801 Modem device in 128-pin TQFP - CX20493 LSD in 28-pin QFN - CX20442 VC in 32-pin TQFP +3.3V operation with +5V tolerant digital inputs Typical power use - CX81801 and CX20493: 209 mW (Normal Mode); 59 mW (Sleep Mode) - CX20442: 5 mW (Normal Mode)
1.3.2
SmartDAA Features
* * * * * * * * * * System side powered DAA operates under poor line current supply conditions Modem Wake-on-Ring Ring detection Line current loss detection Pulse dialing Line-in-use detection during on-hook operation Remote hang-up detection for efficient call termination Extension pickup detection Digital PBX line protection Meets worldwide DC Voltage/Current (VI) masks requirements
1.3.3
Applications
* * * * * * Set top boxes Gaming devices Point of sale terminals Remote monitoring and data collections systems Handheld computers Other embedded systems
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1.4
1.4.1
Technical Overview
General Description
Modem operation, including dialing, call progress, telephone line interface, telephone handset interface, optional voice/speakerphone interface, and host interface functions are supported and controlled through the V.250, V.251, and V.253-compatible command set. The modem hardware connects to the host via a parallel or serial interface as selected by the PARIF input. The OEM adds a crystal circuit, DIB components, telephone line interface, telephone handset/telephony extension interface, voice/speakerphone interface, optional external serial EEPROM, optional external ROM/flash ROM, optional external RAM, and other supporting discrete components as supported by the modem model (Table 1-1) and required by the application to complete the system. Customized modem firmware can be supported by the use of external memory in various combinations, e.g., either external ROM/flash ROM (up to 256 KB), or external serial EEPROM (256 to 32 KB) and external RAM (up to 128 KB). To support country profile addition or modification, external serial EEPROM (256 to 32 KB) can be installed. Customized code can include OEM-defined commands, i.e., identification codes (I3), identifier string (I4), manufacturer identification (+GMI), model identification (+GMM), and revision identification (+GMR), as well as code modification. Parallel interface operation is selected by PARIF input high. Serial interface operation is selected by PARIF input low.
1.4.2
MCU Firmware
MCU firmware performs processing of general modem control, command sets, data modem, error correction and data compression (ECC), fax class 1, fax class 1.0, voice/audio/TAM/speakerphone, worldwide, V.80, and serial DTE/parallel host interface functions according to modem models (Table 1-1). MCU firmware can be customized to include OEM-defined commands, i.e., identification codes (I3), identifier string (I4), manufacturer identification (+GMI), model identification (+GMM), and revision identification (+GMR), as well as code modification. The modem firmware is provided in object code form for the OEM to program into external ROM/flash ROM. The modem firmware may also be provided in source code form under a source code addendum license agreement. External ROM/Flash ROM and RAM must be installed in order to operate the modem with customized firmware.
1.4.3
1.4.3.1
Operating Modes
Data/Fax Modes
Data modem modes perform complete handshake and data rate negotiations. Using modem modulations to optimize modem configuration for line conditions, the modem can connect at the highest data rate that the channel can support from 56 kbps down to 2400 bps with automatic fallback. In V.92/V.90 data modem modes (V.92 models), the modem can receive data from a digital source using a V.92-compatible central site modem at line speeds up to 56 kbps. With PCM upstream enabled (V.92 only), data transmission supports sending data at line
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CX81801-7x/8x SmartV.XX Modem Data Sheet speeds up to 48 kbps. When PCM upstream is disabled, data transmission supports sending data at line speeds up to V.34 rates. This mode can fallback to V.34 mode and to lower rates as dictated by line conditions. The following modes are supported in V.92 models when connected to a V.92compatible server supporting the feature listed. * * Quick connect: Allows quicker subsequent connections to a server by using stored line parameters obtained during the initial connection. Modem-on-Hold: Allows detection and reporting of incoming phone calls on the PSTN with enabled Call Waiting. If the incoming call is accepted by the user, the user has a pre-defined amount of time of holding the data connection for a brief conversation. The data connection resumes upon incoming call termination. PCM upstream: Boosts the upstream data rates. A maximum of 48 kbps is supported when connected to a V.92 server that supports PCM upstream.
*
In V.34 data modem mode (V.92 and V.34 models), the modem can operate in fullduplex, asynchronous modes at line rates up to 33.6 kbps. Automode operation in V.34 is provided in accordance with PN3320 and in V.32 bis in accordance with PN2330. All tone and pattern detection functions required by the applicable ITU or Bell standards are supported. In V.32 bis data modem mode, the modem can operate at line speeds up to 14.4 kbps. In fax modem mode, the modem can operate in half-duplex, synchronous modes and can support Group 3 facsimile send and receive speeds of 14400, 12000, 9600, 7200, 4800, and 2400 bps. Fax data transmission and reception performed by the modem are controlled and monitored through the EIA/TIA-578 Fax Class 1, or T.31 Fax Class 1.0 command interface. Full HDLC formatting, zero insertion/deletion, and CRC generation/checking are provided.
1.4.3.2
V.44 Data Compression
V.44 provides efficient data compression that minimizes the download time for the types of files associated with Internet use. This improvement is most noticeable when browsing and searching the web since HTML text files are highly compressible. (The improved performance amount varies both with the actual format and with the content of individual pages and files.)
1.4.3.3
Worldwide Operation
SmartDAA technology allows a single PCB design and single BOM to be homologated worldwide. Advanced features such as extension pickup detection, remote hang-up detection, line-in-use detection, and digital PBX detection are supported. Country-dependent modem parameters for functions such as dialing, carrier transmit level, calling tone, call progress tone detection, answer tone detection, blacklisting, caller ID, and relay control are programmable. Country code IDs are defined by ITU-T T.35. Embedded ROM code includes default profiles for 29 countries. Additional country profiles can be stored in internal SRAM or external serial EEPROM (request additional country profiles from a Conexant Sales Office). Duplicate country profiles stored in internal SRAM or external serial EEPROM will override the profiles in embedded ROM code. The default countries supported are listed in Table 1-2. Country profiles for CTR-21 countries are TBR-21 compliant.
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CX81801-7x/8x SmartV.XX Modem Data Sheet Table 1-2. Default Countries Supported
Country Country Code 09 0A 0F 16 26 31 3C 3D 42 50 53 57 59 00 61 6C 73 7B 82 8A 8B 9C 9F A0 A5 A6 FE B4 B5 FD Call Waiting Tone Detection (CW) Supported X X X X X X X X X X On-Hook Type 1 Caller ID (CID) Supported X X Off-Hook Type 2 Called ID (CID2) Supported
Australia Austria Belgium Brazil China Denmark Finland France Germany Hong Kong India Ireland Italy Japan Korea Malaysia Mexico Netherlands Norway Poland Portugal Singapore South Africa Spain Sweden Switzerland Taiwan United Kingdom United States Reserved
X X X X
X X X X X X X X X X
X X
X
X X X X X X X X X X X X
X X
X X X X X X X
X
X X X
1.4.3.4
TAM Mode
TAM Mode features include 8-bit linear coding at 8 kHz sample rate. Tone detection/ generation, call discrimination, and concurrent DTMF detection are also supported. TAM Mode is supported by four submodes: * * * * Online Voice Command Mode supports connection to the telephone line or, for S models, a microphone/speaker/handset/headset. Voice Receive Mode supports recording voice or audio data input from the telephone line or, for S models, a microphone/handset/headset. Voice Transmit Mode supports playback of voice or audio data to the telephone line or, for S models, a speaker/handset/headset. Full-duplex Receive and Transmit Mode.
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1.4.3.5
Speakerphone Mode (S Models)
S models include additional telephone handset, external microphone, and external speaker interfaces which support voice and full-duplex speakerphone (FDSP) operation. Hands-free full-duplex telephone operation is supported in Speakerphone Mode under host control. Speakerphone Mode features an advanced proprietary speakerphone algorithm which supports full-duplex voice conversation with acoustic, line, and handset echo cancellation. Parameters are constantly adjusted to maintain stability with automatic fallback from full-duplex to pseudo-duplex operation. The speakerphone algorithm allows position independent placement of microphone and speaker. The host can separately control volume, muting, and AGC in microphone and speaker channels.
1.4.4
Reference Designs
A data/fax/TAM/speakerphone reference design for external modems is available to minimize application design time, reduce development cost, and accelerate market entry. This designs is: * For CX81801 and CX20493: RD01-D660-1xx
A design package is available in electronic form. This package includes schematics, bill of materials (BOM), vendor part list (VPL), board layout files in Gerber format, and complete documentation.
1.5
Hardware Description
SmartDAA technology eliminates the need for a costly analog transformer, relays, and opto-isolators that are typically used in discrete DAA implementations. The programmable SmartDAA architecture simplifies product implementation in worldwide markets by eliminating the need for country-specific components.
1.5.1
CX81801 Modem Device
The CX81801 Modem, packaged in a 128-pin TQFP, includes a Microcontroller (MCU), a Modem Data Pump (MDP), 256 KB internal ROM, 32 KB internal RAM, and SmartDAA interface functions. The CX81801 Modem connects to host via a parallel host (PARIF = high) or a logical V.24 (EIA/TIA-232-E) serial DTE interface (PARIF = low). The CX81801 Modem performs the command processing and host interface functions. The crystal frequency is 28.224 MHz 50 ppm. The CX81801 Modem optionally connects to an external OEM-supplied serial EEPROM over a dedicated 2-line serial interface. The capacity of the EEPROM can be 256 bytes up to 32 KB. The EEPROM can hold information such as firmware configuration customization, and country code parameters. The CX81801 Modem performs telephone line signal modulation/demodulation in a hardware digital signal processor (DSP) which reduces computational load on the host processor. The SmartDAA interface communicates with, and supplies power and clock to, the LSD through the DIB.
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CX81801-7x/8x SmartV.XX Modem Data Sheet The CX81801 optionally connects to external OEM-supplied ROM/flash ROM and RAM over a non-multiplexed 19-bit address bus and 8-bit data bus.
1.5.2
Digital Isolation Barrier
The OEM-supplied Digital Isolation Barrier (DIB) electrically DC isolates the CX81801 from the LSD and telephone line. The modem is connected to a fixed digital ground and operates with standard CMOS logic levels. The LSD is connected to a floating ground and can tolerate high voltage input (compatible with telephone line and typical surge requirements). The DIB transformer couples power and clock from the CX81801 to the LSD. The DIB data channel supports bidirectional half-duplex serial transfer of data, control, and status information between the CX81801 and the LSD over two lines.
1.5.3
CX20493 SmartDAA Line Side Device
The CX20493 SmartDAA Line Side Device (LSD) includes a Line Side DIB Interface (LSDI), a coder/decoder (codec), and a Telephone Line Interface (TLI). The LSDI communicates with, and receives power and clock from, the SmartDAA interface in the CX81801 through the DIB. LSD power is received from the MDP PWRCLKP and PWRCLKN pins via the DIB through a full-wave rectified bridge and capacitive power filter circuit connected to the DIB transformer secondary winding. The CLK input is also accepted from the DIB transformer secondary winding through a capacitor and a resistor in series. Information is transferred between the LSD and the CX81801 through the DIB_P and DIB_N pins. These pins connect to the CX81801 DIB_DATAP and DIB_DATAN pins, respectively, through the DIB. The TLI integrates DAA and direct telephone line interface functions and connects directly to the line TIP and RING pins, as well as to external line protection components. Direct LSD connection to TIP and RING allows real-time measurement of telephone line parameters, such as the telephone central office (CO) battery voltage, individual telephone line (copper wire) resistance, and allows dynamic regulation of the off-hook TIP and RING voltage and total current drawn from the central office (CO). This allows the modem to maintain compliance with U.S. and worldwide regulations and to actively control the DAA power dissipation.
1.5.4
CX20442 Voice Codec
The optional CX20442 Voice Codec (VC), packaged in a 32-pin TQFP, supports voice/full-duplex speakerphone (FDSP) operation with interfaces to a microphone and speaker and to a telephone handset/headset.
1.6
AT Commands
The SmartV.XX Modem supports AT commands for data mode, fax class 1 or 1.0, voice/audio, full-duplex speakerphone (FDSP), V.80 commands, and S Register. See Doc. No. 102184 for a description of the commands.
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CX81801-7x/8x SmartV.XX Modem Data Sheet Data Mode Operation. Data functions operate in response to the AT commands when +FCLASS=0. Default parameters support U.S./Canada operation. Fax Mode Operation. Facsimile functions operate in response to fax class 1 commands when +FCLASS=1 or to fax class 1.0 commands when +FCLASS=1.0. Voice/Audio Operation. Voice/audio functions operate in response to voice/audio commands when +FCLASS=8. Speakerphone Operation. FDSP functions operate in response to speakerphone commands when +FCLASS=8 and +VSP=1 is selected.
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2.
2.1
2.1.1
Technical Specifications
Serial DTE Interface Operation
Automatic Speed/Format Sensing
Command Mode and Data Mode. The modem can automatically determine the speed and format of the data sent from the DTE. The modem can sense speeds of 300, 600, 1200, 2400, 4800, 7200, 9600, 12000, 14400, 16800, 19200, 21600, 24000, 26400, 28800, 38400, 57600, and 115200 bps and the following data formats:
Data Length No. of Character Length Parity (No. of Bits) Stop Bits (No. of Bits) None 7 2 10 Odd 7 1 10 Even 7 1 10 None 8 1 10 Odd 8 1 11* Even 8 1 11* *11-bit characters are sensed, but the parity bit is stripped off during data transmission in Normal and Error Correction modes.
The modem can speed sense data with mark or space parity and configures itself as follows:
DTE Configuration 7 mark 7 space 8 mark 8 space Modem Configuration 7 none 8 none 8 none 8 even
Fax Mode. In V.17 fax mode, the modem can sense speeds up to 115.2 kbps.
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2.2
Parallel Host Bus Interface Operation
Command Mode and Data Mode. The modem can operate at rates up to 230.4 kbps by programming the Divisor Latch in the parallel interface registers if supported by communications software and/or driver. Fax Mode. In V.17 mode, the modem can operate at rates up to 230.4 kbps by programming the Divisor Latch in the parallel interface registers if supported by communications software and/or driver.
2.3
2.3.1
Establishing Data Modem Connections
Dialing
DTMF Dialing. DTMF dialing using DTMF tone pairs is supported in accordance with ITU-T Q.23. The transmit tone level complies with Bell Publication 47001. Pulse Dialing. Pulse dialing is supported in accordance with EIA/TIA-496-A. Blind Dialing. The modem can blind dial in the absence of a dial tone if enabled by the X0, X1, or X3 command.
2.3.2
Telephone Number Directory
The modem supports four telephone number entries in a directory that can be saved in a serial EEPROM. Each telephone number can be up to 32 characters (including the command line terminating carriage return) in length. A telephone number can be saved using the &Zn=x command, and a saved telephone number can be dialed using the DS=n command.
2.3.3
Modem Handshaking Protocol
If a tone is not detected within the time specified in the S7 register after the last digit is dialed, the modem aborts the call attempt.
2.3.4
Call Progress Tone Detection
Ringback, equipment busy, congested tone, warble tone, and progress tones can be detected in accordance with the applicable standard.
2.3.5
Answer Tone Detection
Answer tone can be detected over the frequency range of 2100 40 Hz in ITU-T modes and 2225 40 Hz in Bell modes.
2.3.6
Ring Detection
A ring signal can be detected from a TTL-compatible 15.3 Hz to 68 Hz square wave input.
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2.3.7
Billing Protection
When the modem goes off-hook to answer an incoming call, both transmission and reception of data are prevented for 2 seconds (data modem) or 4 seconds (fax adaptive answer) to allow transmission of the billing tone signal.
2.3.8
Connection Speeds
The modem functions as a data modem when the +FCLASS=0 command is active. Line connection can be selected using the +MS command. The +MS command selects modulation, enables/disables automode, and selects minimum and maximum line speeds (Table 2-1).
2.3.9
Automode
Automode detection can be enabled by the +MS command to allow the modem to connect to a remote modem in accordance with draft PN-3320 for V.34 (Table 2-1). Table 2-1. +MS Command Automode Connectivity
Modulation Bell 103 Bell 212 V.21 V.22 V.22 bis V.23 V.32 V.32 bis V.34 V.90 B103 B212 V21 V22 V22B V23C V32 V32B V34 V90 Possible (, , (), and ) Rates (bps) 300 1200 Rx/75 Tx or 75 Rx/1200 Tx 300 1200 2400 or 1200 1200 9600 or 4800 14400, 12000, 9600, 7200, or 4800 33600, 31200, 28800, 26400, 24000, 21600, 19200, 16800, 14400, 12000, 9600, 7200, 4800, or 2400 56000, 54667, 53333, 52000, 50667, 49333, 48000, 46667, 45333, 44000, 42667, 41333, 40000, 38667, 37333, 36000, 34667, 33333, 32000, 30667, 29333, 28000 56000, 54667, 53333, 52000, 50667, 49333, 48000, 46667, 45333, 44000, 42667, 41333, 40000, 38667, 37333, 36000, 34667, 33333, 32000, 30667, 29333, 28000 48000, 46667, 45333, 44000, 42667, 41333, 40000, 38667, 37333, 36000, 34667, 33333, 32000, 30667, 29333, 28000, 26667, 25333, 24000
V.92 downstream
V92
V.92 upstream
V92
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2.4
Data Mode
The modem enters data mode when a telephone line connection has been established between modems and all handshaking has been completed.
2.4.1
Speed Buffering (Normal Mode)
Speed buffering allows a DTE to send data to, and receive data from, a modem at a speed different than the line speed. The modem supports speed buffering at all line speeds.
2.4.2
Flow Control
DTE-to-Modem Flow Control. If the modem-to-line speed is less than the DTE-tomodem speed, the modem supports XOFF/XON or RTS/CTS flow control with the DTE to ensure data integrity.
2.4.3
Escape Sequence Detection
The +++ escape sequence can be used to return control to the command mode from the data mode. Escape sequence detection is disabled by an S2 Register value greater than 127.
2.4.4
BREAK Detection
The modem can detect a BREAK signal from either the DTE or the remote modem. The \Kn command determines the modem response to a received BREAK signal.
2.4.5
Telephone Line Monitoring
GSTN Cleardown (V.90, V.34, V.32 bis, V.32). Upon receiving GSTN Cleardown from the remote modem in a non-error correcting mode, the modem cleanly terminates the call. Loss of Carrier (V.22 bis and Below). If carrier is lost for a time greater than specified by the S10 register, the modem disconnects.
2.4.6
Fall Forward/Fallback (V.92/V.90/V.34/V.32 bis/V.32)
During initial handshake, the modem will fallback to the optimal line connection within V.92/V.90/V.34/V.32 bis/V.32 mode depending upon signal quality if automode is enabled by the +MS or N1 command. When connected in V.92/V.90/V.34/V.32 bis/V.32 mode, the modem will fall forward or fallback to the optimal line speed within the current modulation depending upon signal quality if fall forward/fallback is enabled by the %E2 command.
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2.4.7
Retrain
The modem may lose synchronization with the received line signal under poor or changing line conditions. If this occurs, retraining may be initiated to attempt recovery depending on the type of connection. The modem initiates a retrain if line quality becomes unacceptable if enabled by the %E command. The modem continues to retrain until an acceptable connection is achieved, or until 30 seconds elapse resulting in line disconnect.
2.4.8
Programmable Inactivity Timer
The modem disconnects from the line if data is not sent or received for a specified length of time. In normal or error-correction mode, this inactivity timer is reset when data is received from either the DTE or from the line. This timer can be set to a value between 0 and 255 seconds by using register S30. A value of 0 disables the inactivity timer.
2.4.9
DTE Signal Monitoring (Serial DTE Interface Only)
DTR#. When DTR# is asserted, the modem responds in accordance with the &Dn and &Qn commands. RTS#. RTS# is used for flow control if enabled by the &K command in normal or errorcorrection mode.
2.5
V.92 Features
Modem-on-Hold, quick connect, and PCM upstream are only available in V.92 models when connecting in V.92 data mode. V.92 features are only available when the server called is a V.92 server that supports that particular feature.
2.5.1
Modem-on-Hold
The Modem-on-Hold (MOH) function enables the modem to place a data call to the Internet on hold while using the same line to accept an incoming or place an outgoing voice call. This feature is available only with a connection to a server supporting MOH. MOH can be executed through either of two methods: * One method is to enable MOH through the +PMH command. With Call Waiting Detection (+PCW command) enabled, an incoming call can be detected while online. Using a string of commands, the modem negotiates with the server to place the data connection on hold while the line is released so that it can be used to conduct a voice call. Once the voice call is completed, the modem can quickly renegotiate with the server back to the original data call. An alternative method is to use communications software that utilizes the Conexant Modem-on-Hold drivers under Windows PC operating systems. Using this method, the software can detect an incoming call, place the data connection on hold, and switch back to a data connection.
*
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2.5.2
Quick Connect
The quick connect function enables the modem to shorten the connect time of subsequent calls to a server supporting quick connect. The quick connect feature is supported by the +PQC command.
2.5.3
PCM Upstream
PCM upstream boosts the upstream data rates between the user and ISP to reduce upload times for large files and email attachments. A maximum of 48 kbps upstream rate is supported with PCM upstream enabled, in contrast to a maximum of 32.2 kbps upstream rate with PCM upstream not enabled. PCM upstream is supported by the +PIG command. PCM upstream is disabled by default.
2.6
2.6.1
Error Correction and Data Compression
V.42 Error Correction
V.42 supports two methods of error correction: LAPM and, as a fallback, MNP 4. The modem provides a detection and negotiation technique for determining and establishing the best method of error correction between two modems.
2.6.2
MNP 2-4 Error Correction
MNP 2-4 is a data link protocol that uses error correction algorithms to ensure data integrity. Supporting stream mode, the modem sends data frames in varying lengths depending on the amount of time between characters coming from the DTE.
2.6.3
V.44 Data Compression
V.44 data compression mode, enabled by the +DS44 command, encodes pages and files associated with Web pages. These files include WEB pages, graphics and image files, and document files. V.44 can provide an effective data throughput rate up to DTE rate for a 56-kbps connection. The improved performance amount varies both with the actual format and with the content of individual pages and files.
2.6.4
V.42 bis Data Compression
V.42 bis data compression mode, enabled by the %Cn command or S46 register, operates when a LAPM connection is established. The V.42 bis data compression employs a "string learning" algorithm in which a string of characters from the DTE is encoded as a fixed length codeword. Two 2-KB dictionaries are used to store the strings. These dictionaries are dynamically updated during normal operation.
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2.6.5
MNP 5 Data Compression
MNP 5 data compression mode, enabled by the %Cn command, operates during an MNP connection. In MNP 5, the modem increases its throughput by compressing data into tokens before transmitting it to the remote modem, and by decompressing encoded received data before sending it to the DTE.
2.7
Telephony Extensions
The following telephony extension features are supported and are typically implemented in designs for set-top box applications and TAM software applications to enhance enduser experience: * * * Line In Use detection Extension Pickup detection Remote Hang-up detection
The telephony extension features are enabled through the -STE command. The -TTE command can be used to adjust the voltage thresholds for the telephony extension features.
2.7.1
Line In Use Detection
The Line In Use Detection feature can stop the modem from disturbing the phone line when the line is already being used. When an automated system tries to dial using ATDT and the phone line is in use, the modem will not go off hook and will respond with the message "LINE IN USE". In the case where no phone line is connected to the modem, the modem will respond with the message "NO LINE".
2.7.2
Extension Pickup Detection
The Extension Pickup Detection feature (also commonly referred as PPD or Parallel phone detection) allows the modem to detect when another telephony device (i.e., fax machine, phone, satellite/cable box) is attempting to use the phone line. When an extension pickup has been detected, the modem will go on-hook and respond with the message "OFF-HOOK INTRUSION". The Remote Hangup Detection feature will cause the modem to go back on-hook and respond with the message "LINE REVERSAL DETECTED" during a data connection when the remote modem is disconnected for abnormal termination reasons (remote phone line unplugged, remote server/modem shutdown). For Voice applications, this method can be used in addition to silence detection to determine when a remote caller has hung up to terminate a voice recording. This feature can be used to quickly drop a modem connection in the event when a user picks up a extension phone line. For example, this feature allows set top boxes with an integrated SmartV.XX modem to give normal voice users the highest priority over the telephone line. This feature can also be used in Telephone Answering Machine applications (TAM). Its main use would be to stop the TAM operation when a phone is picked up.
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2.7.3
Remote Hangup Detection
The Remote Hangup Detection feature will cause the modem to go back on-hook and respond with the message "LINE REVERSAL DETECTED" during a data connection when the remote modem is disconnected for abnormal termination reasons (remote phone line unplugged, remote server/modem shutdown). For Voice applications, this method can be used in addition to silence detection to determine when a remote caller has hung up to terminate a voice recording.
2.8
Fax Class 1 and Fax Class 1.0 Operation
Facsimile functions operate in response to fax class 1 commands when +FCLASS=1 or to fax class 1.0 commands when +FCLASS=1.0. In the fax mode, the on-line behavior of the modem is different from the data (non-fax) mode. After dialing, modem operation is controlled by fax commands. Some AT commands are still valid but may operate differently than in data modem mode. Calling tone is generated in accordance with T.30.
2.9
Point-of-Sales Support
Point-of-Sales (POS) terminals usually need to exchange a small amount of data in the shortest amount of time. Low speed modulations such as Bell212A or V.22 are still mainly used in POS applications. Additionally, new non-standard sequences have been developed to better support POS applications. Industry standard and shortened answer tone B103 and V.21 are supported, as well as FastPOS (V.29) and V.22 Fast Connect. POS terminal modulations are supported by the $F command.
2.10
Voice/Audio Mode
Voice and audio functions are supported by the Voice Mode. Voice Mode includes four submodes: Online Voice Command Mode, Voice Receive Mode, Voice Transmit Mode and Full-Duplex Receive and Transmit Mode.
2.10.1
Online Voice Command Mode
This mode results from the connection to the telephone line or a voice/audio I/O device (e.g., microphone, speaker, or handset) through the use of the +FCLASS=8 and +VLS commands. After mode entry, AT commands can be entered without aborting the connection.
2.10.2
Voice Receive Mode
This mode is entered when the +VRX command is active in order to record voice or audio data input at the RIN pin, typically from a microphone/handset or the telephone line. Received analog voice samples are converted to digital form and compressed for reading by the host. AT commands control the codec bits-per-sample rate.
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CX81801-7x/8x SmartV.XX Modem Data Sheet Received analog mono audio samples are converted to digital form and formatted into 8bit unsigned linear PCM format for reading by the host. AT commands control the bit length and sampling rate. Concurrent DTMF/tone detection is available at the 8 kHz sample rate.
2.10.3
Voice Transmit Mode
This mode is entered when the +VTX command is active in order to playback voice or audio data to the TXA output, typically to a speaker/handset or to the telephone line. Digitized voice data is decompressed and converted to analog form at the original compression quantization sample-per-bits rate then output to the TXA output. Digitized audio data is converted to analog form then output to the TXA output.
2.10.4
Full-Duplex Receive and Transmit Mode
This mode is entered when the +VTR command is active in order to concurrently receive and transmit voice.
2.10.5
Audio Mode
The audio mode enables the host to transmit and receive 8-bit audio signals. In this mode, the modem directly accesses the internal analog-to-digital (A/D) converter (ADC) and the digital-to-analog (D/A) converter (DAC). Incoming analog audio signals can then be converted to digital format and digital signals can be converted to analog audio output.
2.10.6
Tone Detectors
The tone detector signal path is separate from the main received signal path thus enabling tone detection to be independent of the configuration status. In Tone Mode, all three tone detectors are operational.
2.10.7
Speakerphone Mode
Speakerphone mode is controlled in voice mode with the following commands: Use Speakerphone After Dialing or Answering (+VSP=1). +VSP=1 selects speakerphone mode while in +FCLASS=8 mode. Speakerphone operation is entered during Voice Online Command mode after completing dialing or answering. Speakerphone Settings. The +VGM and +VGS commands can be used to control the microphone gain and speaker volume, respectively. VGM and +VGS commands are valid only after the modem has entered the Voice Online mode while in the +VSP=1 setting.
2.11
V.80 Synchronous Access Mode (SAM) - Video Conferencing
V.80 Synchronous Access Mode between the modem and the host/DTE is provided for host-controlled communication protocols, e.g., H.324 video conferencing applications. Voice-call-first (VCF) before switching to a videophone call is also supported.
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2.12
Full-Duplex Speakerphone (FDSP) Mode (S Models)
The modem operates in FDSP mode when +FCLASS=8 and +VSP=1 (Section 2.10.7). In FDSP Mode, speech from a microphone or handset is converted to digital form, shaped, and output to the telephone line through the line interface circuit. Speech received from the telephone line is shaped, converted to analog form, and output to the speaker or handset. Shaping includes both acoustic and line echo cancellation.
2.13
Caller ID
Both Type I Caller ID (On-Hook Caller ID) and Type II Caller ID (Call Waiting Caller ID) are supported for U.S. and many other countries (see Section 2.14). Both types of Caller ID are enabled/disabled using the +VCID command. Call Waiting Tone detection must be enabled using the +PCW command to detect and decode Call Waiting Caller ID. When enabled, caller ID information (date, time, caller code, and name) can be passed to the DTE in formatted or unformatted form. Inquiry support allows the current caller ID mode and mode capabilities of the modem to be retrieved from the modem. Type II Caller ID (Call Waiting Caller ID) detection operates only during data mode in V.92, V.90, V.34, V.32bis, or V.32.
2.14
Worldwide Country Support
Internal modem firmware supports 29 country profiles (see Section 1.3.2). These country profiles include the following country-dependent parameters: * * * * * * * * * * Dial tone detection levels and frequency ranges. DTMF dialing parameters: Transmit output level, DTMF signal duration, and DTMF interdigit interval. Pulse dialing parameters: Make/break times, set/clear times, and dial codes are programmable Ring detection frequency range. Type I and Type II Caller ID detection are supported for many countries. Contact your local Conexant sales office for additional country support. Blind dialing enabled/disable. Carrier transmit level (through S91 for data and S92 for fax). The maximum, minimum, and default values can be defined to match specific country and DAA requirements. Calling tone is generated in accordance with V.25. Calling tone may be toggled (enabled/disabled) by inclusion of a "^" character in a dial string. It may also be disabled. Frequency and cadence of tones for busy, ringback, congested, warble, dial tone 1, and dial tone 2. Answer tone detection period.
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Blacklist parameters. The modem can operate in accordance with requirements of individual countries to prevent misuse of the network by limiting repeated calls to the same number when previous call attempts have failed. Call failure can be detected for reasons such as no dial tone, number busy, no answer, no ringback detected, voice (rather than modem) detected, and key abort (dial attempt aborted by user). Actions resulting from such failures can include specification of minimum inter-call delay, extended delay between calls, and maximum numbers of retries before the number is permanently forbidden ("blacklisted").
These country profiles may be altered or customized by modifying the country-dependent parameters. Additional profiles may also be included. There are two ways to add or modify profiles: * * Incorporating additional or modified profiles into external flash ROM containing the entire modem firmware code. Linking additional or modified profiles from an external serial EEPROM (needed only if the external flash ROM capacity is exceeded.
Please contact an FAE at the local Conexant sales office if a country code customization is required.
2.15
2.15.1
Diagnostics
Commanded Tests
Diagnostics are performed in response to test commands. Analog Loopback (&T1 Command). Data from the local DTE is sent to the modem, which loops the data back to the local DTE. DTMF Generation (%TT0 Command). Continuous DTMF tones are generated by the DSP and output through the DAA. Tone Generation (%TT3 Command). Continuous tones are generated by the DSP and output through the DAA.
2.15.2
Power On Reset Tests
Upon power on, the modem performs tests of the modem and internal RAM. If the modem or internal RAM test fails, the TMIND# output is pulsed as follows (Figure 2-1): * * Internal RAM test fails: One pulse cycle (pulse cycle = 0.5 sec. on, 0.5 sec. off) every 1.5 seconds. Modem device test fails: Three pulse cycles every 1.5 seconds.
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CX81801-7x/8x SmartV.XX Modem Data Sheet Figure 2-1. TMIND# Test Results Pulse Cycles
Internal RAM Fails
Pulse Cycle 1.5 Sec
0
.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Modem Device Fails
Pulse Cycle 1.5 Sec
0
.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
102179_004
2.16
Low Power Sleep Mode
Sleep Mode Entry. The modem enters the low power sleep mode when no line connection exists and no host activity occurs for the period of time specified in the S24 register. All modem circuits are turned off except the internal clock circuitry in order to consume reduced power while being able to immediately wake up and resume normal operation. Wake-up. Wake-up occurs when a ring is detected on the telephone line, the host writes to the modem (parallel interface), or the DTE sends a character to the modem (serial interface).
2-12
Conexant
102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet
3.
3.1
3.1.1
3.1.1.1
Hardware Interface
CX81801 Modem Hardware Pins and Signals
Common to Parallel and Serial Interface Configurations
LSD Interface (Through DIB)
The DIB interface signals are: * * * * Clock and Power Positive (PWRCLKP); output Clock and Power Negative (PWRCLKN); output Data Positive (DIB_DATAP); input/output Data Negative (DIB_DATAN); input/output
3.1.1.2
Call Progress Speaker Interface
The call progress speaker interface signal is: * Digital speaker output (DSPKOUT); output DSPKOUT is a square wave output in Data/Fax mode used for call progress or carrier monitoring. This output can be optionally connected to a low-cost on-board speaker, e.g., a sounducer, or to an analog speaker circuit.
3.1.1.3
Voice Relay Interface (S Models)
The voice relay interface signal is: * Voice Relay Control (VOICE#); output
3.1.1.4
Serial EEPROM Interface
A 2-line serial interface to an optional serial EEPROM is supported. The interface signals are: * * Bidirectional Data input/output (NVMDATA) Clock output (NVMCLK)
The EEPROM can hold information such as firmware customization, and country code parameters. Data stored in EEPROM takes precedence over the factory default settings. Note: This information is usually stored in flash ROM; serial EEPROM is required only if storage is required for more than 31 country profiles. The EEPROM size can range from 2 Kb (256 x 8) to 256 Kb (32K x 8). A 2 Kb EEPROM must be 100 kHz or 400 kHz; higher capacity EEPROMs must be 400 kHz.
102199B
Conexant
3-1
CX81801-7x/8x SmartV.XX Modem Data Sheet
3.1.1.5
External Bus Interface
The external bus optionally connects to OEM-supplied external memory: * * * * * * * * Up to 4 Mb (512K x 8) ROM/flash ROM Up to 1 Mb (128K x 8) RAM Eight bidirectional Data lines (D0-D7) 19 Address output lines (A0-A18) Read Enable output (READ#) Write Enable output (WRITE#) ROM Chip Select output (ROMSEL#) RAM Chip Select output (RAMSEL#)
The non-multiplexed external bus interface signals are:
3.1.2
3.1.2.1
Serial Interface Configuration Only
Serial DTE Interface and Indicator Outputs (PARIF = Low)
A V.24/EIA/TIA-232-E logic-compatible serial DTE interface is selected when the PARIF input is low. The supported DTE interface signals are: * * * * * * * * * * * * * * * * Serial Transmit Data input (TXD#) Serial Receive Data output line (RXD#) Clear to Send output (CTS#) Data Set Ready output (DSR#) Received Line Signal Detector (RLSD#) Test Mode output (TM#) Ring Indicator (RI#) Data Terminal Ready control input (DTR#) Request to Send control input (RTS#) Receive Data Clock (RXCLK#) Transmit Data Clock (TXCLK#) External Clock (XTCLK#) Auto Answer indicator output (AAIND#) Data Terminal Ready indicator output (DTRIND#) Test Mode indicator output (TMIND#) Off-hook indicator output (OHIND#)
Additional clock signals provided for synchronous mode are:
The following indicator output lines are also supported:
3-2
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102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet
3.1.3
Parallel Interface Configuration Only (PARIF = High)
A 16550A UART-compatible parallel host bus interface is selected when the PARIF input is high.
3.1.3.1
Parallel Host Bus Interface
The parallel host interface signals are: * * * * * * Host Reset control input line (RESET#) Host Chip Select control input (HCS#) Host Read control input (HRD#) and Host Write control input (HWT#) Host Interrupt output line (HINT) Three Host Address input lines (HA0-HA2) Eight Host Data lines (HD0-HD7)
3.1.4
CX81801 Modem Interface Signals
CX81801 Modem 128-pin TQFP hardware interface signals for parallel interface are shown by major interface in Figure 3-1, are shown by pin number in Figure 3-2, and are listed by pin number in Table 3-1. The Smart Modem hardware interface signals for parallel interface are defined in Table 3-2. CX81801 Modem 128-pin TQFP hardware interface signals for serial interface are shown by major interface in Figure 3-3, are shown by pin number in Figure 3-4, and are listed by pin number in Table 3-3. CX81801 Modem hardware interface signals for serial interface are defined in Table 3-4. I/O types are defined in Table 3-5. DC electrical characteristics are listed in Table 3-6.
102199B
Conexant
3-3
CX81801-7x/8x SmartV.XX Modem Data Sheet
Figure 3-1. CX81801 Modem Hardware Signals for Parallel Interface (PARIF = High)
CRYSTAL CIRCUIT 114 115 113 61 49 111 240K +3.3V 57 47 XTLI XTLO CLKIN CLKOUT XCLK DV1TP LPO NOXYCK LINE_SEL (PE7) 23 47K +3.3V 47K +3.3V NC 47K +3.3V NC NC NC
RESERVED (PA5) RESERVED (PA4) RESERVED (PE5) RESERVED (PE2) RESERVED (PA3)
31 29 21 17 28 14
NC NC NC
NC
5
PARIF
RESERVED (PE0)
NC +3.3V
9 117 34 11 13 12 109 6 7 8 122 123 125 126 127 1 3 4
STPMODE# (PD3) NMI# RESET# HCS# (PD4) HRD# (PD6) HWT# (PD5) HINT (PB7) HA0 (PD0) HA1 (PD1) HA2 (PD2) HD0 (PC0) HD1 (PC1) HD2 (PC2) HD3 (PC3) HD4 (PC4) HD5 (PC5) HD6 (PC6) HD7 (PC7)
VOICE# (PE1) HS_LCS (PE4)
16 19
VOICE# HS_LCS
DAA
DSPKOUT PWRCLKP PWRCLKN DIB_DATAP DIB_DATAN
98 96 97 93 94
SPEAKER CIRCUIT
DIGITAL ISOLATION BARRIER (DIB)
HOST PARALLEL BUS
IASLEEP (P_PF05) M_CLK (P_PB00) SR2CLK (P_PGP05) SA2CLK (P_PX05) SR3OUT SR3IN (P_PX01) SR2IO (P_PX06)
50 37 92 38 35 36 39
SLEEP M_CLKIN M_SCK M_STROBE M_TXSIN M_RXOUT M_CNTRLSIN
CX20442 VOICE CODEC (VC) (OPTIONAL)
NC
24 22 26 110 121 45 46 27 32 101 55 54 56 51 59 52 41 42 43 60 2 15 40 58 78 100 108 116 124 20 53 85 10 25 30 44 48 68 90 95 103 112 120 128
RESERVED (PA0) RESERVED (PE6) RESERVED (PA1) TESTP PHS2 SR4IN PD7 RESERVED (PA2) RESERVED (PA6) RESERVED (PB1) RESERVED (P_PA00) RESERVED (P_PA04) RESERVED (P_PA05) RESERVED (P_PB01) RESERVED (BD2CLK) RESERVED (P_GP00) P_PX00 P_PX02 P_PX03 VGG VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD_CORE VDD_CORE VDD_CORE GND GND GND GND GND GND GND GND GND GND GND GND
CX81801 Smart Modem 128-Pin TQFP Parallel Interface (PARIF = High)
NVMCLK (PA7) NVMDATA (PE3)
33 18
EEPROM (OPTIONAL)
+3.3V or +5V
+3.3V
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 (PB0) A17 (PB4) A18 (PB5) D0 D1 D2 D3 D4 D5 D6 D7 WRITE# READ# ROMSEL# (PB2) RAMSEL# (PB3) EXT_RES# (PB6) PLLVDD
71 72 73 74 75 76 77 79 80 81 84 86 87 88 89 91 99 105 106 62 63 64 65 66 67 69 70 118 119 102 104 107 82 0.1 uF NC
EXTERNAL MEMORY
+3.3V
PLLGND
83
102199_003
3-4
Conexant
102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet
Figure 3-2. CX81801 Modem 128-Pin TQFP Pin Signals for Parallel Interface (PARIF = High)
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
GND HD4 (PC4) HD3 (PC3) HD2 (PC2) VDD HD1 (PC1) HD0 (PC0) PHS2 GND READ# WRITE# NMI# VDD XTLO XTLI CLKIN GND DV1TP TESTP HINT (PB7) VDD EXT_RES# (PB6) A18 (PB5) A17 (PB4) RAMSEL# (PB3) GND
HD5 (PC5) VDD HD6 (PC6) HD7 (PC7) PARIF HA0 (PD0) HA1 (PD1) HA2 (PD2) STPMODE# (PD3) GND HCS# (PD4) HWT# (PD5) HRD# (PD6) RESERVED (PE0) VDD VOICE# (PE1) RESERVED (PE2) NVMDATA (PE3) HS_LCS (PE4) VDD_CORE RESERVED (PE5) RESERVED (PE6) LINE_SEL (PE7) RESERVED (PA0) GND RESERVED (PA1) RESERVED (PA2) RESERVED (PA3) RESERVED (PA4) GND RESERVED (PA5) RESERVED (PA6) NVMCLK (PA7) RESET# SR3OUT SR3IN (P_PX01) M_CLK (P_PB00) SA2CLK (P_PX05)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
ROMSEL# (PB2) RESERVED (PB1) VDD A16 (PB0) DSPKOUT PWRCLKN PWRCLKP GND DIB_DATAN DIB_DATAP SR2CLK (P_PGP05) A15 GND A14 A13 A12 A11 VDD_CORE A10 PLLGND PLLVDD A9 A8 A7 VDD A6 A5 A4 A3 A2 A1 A0 D7 D6 GND D5 D4 D3
CX81801 Parallel Interface (PARIF Pin = High)
VDD P_PX00 P_PX02 P_PX03
GND XCLK IASLEEP (P_PF05) RXCLK (P_PB01) XTCLK (GP00) VDD_CORE TXCLK (P_PA04) RESERVED (P_PA00) RESERVED (P_PA05)
SR2IO (P_PX06)
GND SR4IN PD7 NOXYCK
LPO VDD RESERVED (BD2CLK)
VGG CLKOUT
D0 D1 D2
102199_004
102199B
Conexant
3-5
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-1. CX81801 Modem 128-Pin TQFP Pin Signals for Parallel Interface (PARIF = High)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Signal Label HD5 (PC5) VDD HD6 (PC6) HD7 (PC7) PARIF HA0 (PD0) HA1 (PD1) HA2 (PD2) STPMODE# (PD3) GND HCS# (PD4) HWT# (PD5) HRD# (PD6) RESERVED (PE0) VDD VOICE# (PE1) RESERVED (PE2) NVMDATA (PE3) HS_LCS (PE4) VDD_CORE CELDATA (PE5) SSD_RING# (PE6) LINE_SEL (PE7) RESERVED (PA0) GND SSD_INT (PA1) PA2 RESERVED (PA3) RESERVED (PA4) GND RESERVED (PA5) PA6 P I/O I/O I I I I I G I I I O P O O I/O I P I/O O I O G O I/O I I G I I/O I/O I/O I/O Type Ith/Ot8 PWR Ith/Ot8 Ith/Ot8 Itpu Ithpd/Ot2 Ithpd/Ot2 Ithpd/Ot2 Ith/Ot2 GND It Ithpu Ithpu It/Ot8 PWR It/Ot2 It/Ot2 It/Ot2 It/Ot2 PWR It/Ot2 It/Ot2 It/Ot8 It/Ot2 GND It/Ot2 It/Ot2 Itpu/Ot2 Itpu/Ot2 GND It/Ot2 It/Ot2 +3.3V HB: HD6 HB: HD7 NC (parallel interface) HB: HA0 HB: HA1 HB: HA2 NC GND HB: CS# HB: WT# HB: RD# NC +3.3V DAA: VOICE# RESERVED NVRAM: SDA GND through 47 K Internal core voltage +3.3V through 47 K NC +3.3V through 47 K NC GND NC NC RESERVED RESERVED GND +3.3V through 47 K NC Interface HB: HD5 Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 D3 D4 D5 GND D6 D7 A0 A1 A2 A3 A4 A5 A6 VDD A7 A8 A9 PLLVDD PLLGND A10 VDD_CORE A11 A12 A13 A14 GND A15 SR2CLK (P_PGP05) DIB_DATAP DIB_DATAN GND PWRCLKP Signal Label I/O I/O I/O I/O G I/O I/O O O O O O O O P O O O P G O P O O O O G O I I/O I/O G O I/O Type Ith/Ot2 Ith/Ot2 Ith/Ot2 GND Ith/Ot2 Ith/Ot2 It/Ot8 It/Ot8 It/Ot8 It/Ot8 It/Ot8 It/Ot8 It/Ot8 PWR It/Ot8 It/Ot8 It/Ot8 PWR GND It/Ot8 PWR It/Ot8 It/Ot8 It/Ot8 It/Ot8 GND It/Ot8 Itpu/Ot2 Idd/Odd Idd/Odd GND Odpc Interface EB: D3 EB: D4 EB: D5 GND EB: D6 EB: D7 EB: A0 EB: A1 EB: A2 EB: A3 EB: A4 EB: A5 EB: A6 +3.3V EB: A7 EB: A8 EB: A9 +3.3V and to GND through 0.1 F GND EB: A10 Internal core voltage EB: A11 EB: A12 EB: A13 EB: A14 GND EB: A15 VC: M_SCK DIB: Data Pos. Channel DIB: Data Neg. Channel GND DIB: Transformer primary winding nondotted terminal DIB: Transformer primary winding dotted terminal Speaker Circuit EB: A16 +3.3V NC EB: ROM CE# GND EB: RAM CS# EB: A17 EB: A18 NC +3.3V HB: HINT NC
33
NVMCLK (PA7)
O
It/Ot2
NVRAM: SCL
97
PWRCLKN
O
Odpc
34 35 36 37 38 39 40 41 42 43 44 45 46
RESET# SR3OUT SR3IN (P_PX01) M_CLK (P_PB00) SA2CLK (P_PX05) SR2IO (P_PX06) VDD P_PX00 P_PX02 P_PX03 GND SR4IN PD7
I O I O I O P I/O I/O I/O G I I/O
It Ot2 Itk/Ot2 It/Ot2 Itpu/Ot2 It/Ot2 PWR It/Ot8 Itpu/Ot2 Itpu/Ot2 GND Itk It/Ot2
HB: RESET# VC: M_TXSIN VC: M_RXOUT VC: M_CLKIN VC: M_STROBE VC: M_CNTRLSIN +3.3V NC NC NC GND NC NC
98 99 100 101 102 103 104 105 106 107 108 109 110
DSPKOUT A16 (PB0) VDD RESERVED (PB1) ROMSEL# (PB2) GND RAMSEL# (PB3) A17 (PB4) A18 (PB5) EXT_RES# (PB6) VDD HINT (PB7) TESTP
O O P O O G O O O O P O I
It/Ot2 It/Ot2 PWR It/Ot2 Ot2 GND It/Ot2 It/Ot2 It/Ot2 It/Ot2 PWR It/Ot8 Itpu
3-6
Conexant
102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-1. CX81801 Modem 128-Pin TQFP Pin Signals for Parallel Interface (PARIF = High) (Continued)
Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Signal Label NOXYCK GND XCLK IASLEEP (P_PF05) RESERVED (P_PB01) RESERVED (GP00) VDD_CORE RESERVED (P_PA04) RESERVED (P_PA00) RESERVED (P_PA05) LPO VDD RESERVED (BD2CLK) VGG CLKOUT D0 D1 I G O O I/O I/O P I/O I/O I/O I P O P O I/O I/O I/O I/O Type Itpu GND It/Ot2 Ot2 Itpu/Ot2 It/Ot2 PWR Itpu/Ot2 Itpu/Ot2 Itk/Ot2 Itpu/Ot2 PWR Itpu/Ot2 PWRG It/Ot2 Ith/Ot2 IthOt2 GND GND NC VC: SLEEP NC NC Internal core voltage NC NC NC +3.3V through 240 K +3.3V NC +3.3V or +5V NC EB: D0 EB: D1 EB: D2 Interface Pin 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Signal Label DV1TP GND CLKIN XTLI XTLO VDD NMI# WRITE# READ# GND PHS2 HD0 (PC0) HD1 (PC1) VDD HD2 (PC2) HD3 (PC3) HD4 (PC4) GND I G I I O P I O O G O I/O I/O P I/O I/O I/O G I/O I/O Type Itpu GND It Ix Ox PWR Ithpu It/Ot2 It/Ot2 GND Ot2 Ith/Ot8 Ith/Ot8 PWR Ith/Ot8 Ith/Ot8 Ith/Ot8 GND GND GND Crystal Circuit Crystal Circuit +3.3V +3.3V EB: WRITE# EB: READ# GND NC HB: HD0 HB: HD1 +3.3V HB: HD2 HB: HD3 HB: HD4 GND Interface Clock Select
64 D2 I/O Ith/Ot2 Notes: 1. I/O Types: See Table 3-5. 2. Interface Legend: DIB Digital Isolation Barrier EB Expansion Bus HB Host Bus NC No internal pin connection VC Voice Codec
102199B
Conexant
3-7
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High)
Label XTLI, XTLO 114, 115 Pin I/O I, O I/O Type System Ix, Ox Crystal In and Crystal Out. If an external 28.224 MHz crystal circuit is used instead of an external clock circuit, connect XTLI and XTLO to the external crystal circuit and connect CLKIN to digital ground (GND). Clock In. If an external 28.224 MHz clock circuit is used instead of an external crystal circuit, connect CLKIN to the clock output and leave XTLI and XTLO open. Clock Out. 28.224 MHz output clock. Leave open. Clock Input Select. This input is used to choose the clock input. Connect to +3.3V or leave open to select XTLI as the clock input. Connect to GND to select CLKIN as the clock input. Parallel/Serial Interface Select. PARIF input high (open) selects parallel host interface operation (see this table); PARIF low (GND) selects serial DTE interface operation (see Table 3-4). Line Interface Select. Selects telephone line interface. Connect to +3.3V though 47 K. Stop Mode. Not used. Leave open. Non-Maskable Interrupt. Not used. Connect to +3.3V. Reset. The active low RESET# input resets the Smart Modem logic, and restores the saved configuration from serial EEPROM or returns the modem to the factory default values if NVRAM is not present. RESET# low holds the modem in the reset state; RESET# going high releases the modem from the reset state. After application of VDD, RESET# must be held low for at least 15 ms after the VDD power reaches operating range. The modem device set is ready to use 25 ms after the low-to-high transition of RESET#. For parallel Interface, connect RESET# input to the host bus RESET line through an inverter. VGG VDD 60 2, 15, 40, 58, 78, 100, 108, 116, 124 20, 53, 85 10, 25, 30, 44, 48, 68, 90, 95, 103, 112, 120, 128 57 47 P P PWRG PWR I/O Signaling Voltage Source. Connect to +3.3V for +3.3V inputs, or to +5V for +5V inputs. Digital Supply Voltage. Connect to VCC (+3.3V, filtered). Signal Name/Description
CLKIN
113
I
It
CLKOUT DV1TP
61 111
O I
It/Ot2 Itpu
PARIF
5
I
Itpu
LINE_SEL (PE7) STPMODE# (PD3) NMI# RESET#
23 9 117 34
I I I I
It/Ot8 Ith/Ot2 Ithpu It
VDD_CORE GND
P G
PWR GND
Core Voltage. Internal core voltage. Digital Ground. Connect to digital ground (GND).
LPO NOXYCK
I I
I/O Itpu
Low Power Oscillator. Connect to +3.3V through 240 K. Disable XCLK Output. When low, disables XCLK output (reduces internal power consumption). When high, enables XCLK output. Connect to GND. PLL Circuit Digital Supply Voltage. Connect to +3.3V and to GND through 0.1 F.
PLLVDD PLLGND NVMCLK (PA7) NVMDATA (PE3)
82 83 33 18
P G O I/O
PWR
GND PLL Circuit Digital Ground. Connect to GND. Serial EEPROM (NVRAM) Interface It/Ot2 It/Ot2 NVRAM Clock. NVMCLK output high enables the EEPROM. Connect to EEPROM SCL pin. NVRAM Data. The NVMDATA pin supplies a serial data interface to the EEPROM. Connect to EEPROM SDA pin and to +3.3V through 10 K.
3-8
Conexant
102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High) (Continued)
Label DSPKOUT 98 Pin I/O O I/O Type Speaker Interface It/Ot2 Signal Name/Description
Modem Speaker Digital Output. The DSPKOUT digital output reflects the received analog input signal digitized to TTL high or low level by an internal comparator. DIB Interface Clock and Power Positive. Provides clock and power to the LSD. Connect to DIB transformer primary winding non-dotted terminal. Clock and Power Negative. Provides clock and power to the LSD. Connect to DIB transformer primary winding dotted terminal. Data Positive. Transfers data, control, and status information between the Smart Modem and the LSD. Connect to LSD through DIB data positive channel components.
PWRCLKP PWRCLKN DIB_DATAP
96 97 93
O O I/O
Odpc Odpc Idd/Odd
DIB_DATAN
94
I/0
Idd/Odd
Data Negative. Transfers data, control, and status information between the Smart Modem and the LSD. Connect to LSD through DIB data negative channel components. External Bus Interface Address Lines 0-18. A0-A18 are the address output lines used to access external memory; up to 4 Mb (512 KB) ROM/flash ROM using A0-A18 and up to 1 Mb (128 KB) RAM using A0-A16. The 256 KB base modem ROM code is located in the 0-256 KB address range. Data Line 0-7. D0-D7 are the bidirectional external memory bus data lines. Read Enable. READ# output low enables data transfer from the selected device to the D0-D7 lines. Write Enable. WRITE# output low enables data transfer from the D0-D7 lines to the selected device. ROM Select. ROMSEL# (PB2, ES3) output low selects the external ROM/flash ROM. RAM Select. RAMSEL# (PB3, ES2) output low selects the external RAM. Reserved. PB1 (ES4) is used internally. Leave open.
A0-A9, A10-A15, A16 (PB0), A17 (PB4), A18 (PB5) D0-D7 READ# WRITE# ROMSEL# (PB2) RAMSEL# (PB3) RESERVED (PB1) EXT_RES# (PB6)
71-77, 79-81, 84, 86-89, 91, 99, 105, 106 62-67, 69-70 119 118 102 104 101 107
O, O, O, O, O I/O O O O O O O
It/Ot8, It/Ot8, It/Ot2, It/Ot2, It/Ot2 Ith/Ot2 It/Ot2 It/Ot2 Ot2 It/Ot2 It/Ot2 It/Ot2
External Device Reset. Active low reset for external devices. Leave open if not used. CX20442 VC Interface Modem Sleep. Connect to VC SLEEP pin. Master Clock Output. Connect to VC M_CLKIN pin. Voice Serial Clock input. Connect to VC M_SCK pin. Voice Serial Frame Sync Input. Connect to VC M_STROBE pin. Voice Serial Transmit Data Output. Connect to VC M_TXSIN pin. Voice Serial Receive Data Input. Connect to VC M_RXOUT pin. Voice Control Output. Connect to VC M_CNTRLSIN pin.
IASLEEP (P_PF05) M_CLK (P_PB00) SR2CLK (P_PGP05) SA2CLK (P_PX05) SR3OUT SR3IN (P_PX01) SR2IO (P_PX06)
50 37 92 38 35 36 39
O O I I O I O
Ot2 It/Ot2 Itpu/Ot2 Itpu/Ot2 Ot2 Itk/Ot2 It/Ot2
102199B
Conexant
3-9
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High) (Continued)
Label HCS# (PD4) HWT# (PD5) 11 12 Pin I I I/O I/O Type Parallel Host Interface It Ithpu Signal Name/Description
Host Bus Chip Select. HCS# input low enables the MCU host bus interface. Host Bus Write. HWT# is an active low, write control input. When HCS# is low, HWT# low allows the host to write data or control words into a selected MCU register. Host Bus Read. HRD# is an active low, read control input. When HCS# is low, HRD# low allows the host to read status information or data from a selected MCU register. Host Bus Interrupt. HINT output is set high when the receiver error flag, received data available, transmitter holding register empty, or modem status interrupt is asserted. HINT is reset low upon the appropriate interrupt service or master reset operation. Host Bus Address Lines 0-2. During a host read or write operation with HCS# low, HA0-HA2 select an internal MCU 16550A-compatible register. Host Bus Data Lines 0-7. HD0-HD7 are three-state input/output lines providing bidirectional communication between the host and the MCU. Data, control words, and status information are transferred over HD0-HD7.
HRD# (PD6)
13
I
Ithpu
HINT (PB7)
109
O
It/Ot8
HA0-HA2 (PD0-PD2) HD0-HD7 (PC0-PC7)
6-8
I
Ithpd/Ot2
122-123, 125127, 1, 3-4
I/O
Ith/Ot8
3-10
Conexant
102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High) (Continued)
Label VOICE# (PE1) HS_LCS (PE4) 16 19 Pin O I I/O I/O Type DAA Interface It/Ot2 It/Ot2 Signal Name/Description
Voice Relay Control. This output (typically active low) used to control the normally open voice relay. Handset Line Current Sense. LCS is an active high input that indicates a handset off-hook status. Not required for data/fax/voice/speakerphone operation. If not used, connect to GND through 47 K. Not Used Test. Used for factory test only. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Reserved. Connect to +3.3V though 47 K. Not Used. Leave open. Not Used. Leave open. Reserved. Connect to +3.3V though 47 K. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open.
TESTP XCLK PHS2 SR4RIN PA2 PA6 PD7 P_PX00 P_PX02 P_PX03 RESERVED (PA0) RESERVED (PA1) RESERVED (PA3) RESERVED (PA4) RESERVED (PA5) RESERVED (PE0) RESERVED (PE2) RESERVED (PE5) RESERVED (PE6) RESERVED (GP00) RESERVED (P_PA00) RESERVED (P_PA04) RESERVED (P_PA05) RESERVED (P_PB01)
110 49 121 45 27 32 46 41 42 43 24 26 28 29 31 14 17 21 22 52 55 54 56 51
I O O I I O I/O I/O I/O I/O O O I I I O O I/O O I/O I/O I/O I/O I/O
Itpu It/Ot2 Ot2 Itk It/Ot2 It/Ot2 It/Ot2 It/Ot8 Itpu/Ot2 Itpu/Ot2 It/Ot2 It/Ot2 Itpu/Ot2 Itpu/Ot2 It/Ot2 It/Ot8 It/Ot2 It/Ot2 It/Ot2 It/Ot2 Itpu/Ot2 Itpu/Ot2 Itk/Ot2 Itpu/Ot2
RESERVED 59 I/O Itpu/Ot2 Not Used. Leave open. (P_BD2CLK) Notes: 1. I/O Types: See Table 3-5. 2. Interface Legend: DIB Digital Isolation Barrier EB Expansion Bus HB Host Bus NC No internal pin connection VC Voice Codec RESERVED = No external connection allowed (may have internal connection).
102199B
Conexant
3-11
CX81801-7x/8x SmartV.XX Modem Data Sheet
Figure 3-3. CX81801 Modem Hardware Signals for Serial Interface (PARIF = Low)
CRYSTAL CIRCUIT 114 115 113 61 49 111 240K +3.3V 57 47 XTLI XTLO CLKIN CLKOUT XCLK DV1TP RESERVED (PA4) LPO NOXYCK RESERVED (PE5) RESERVED (PE2) PARIF RESERVED (PA3) NC +3.3V RESET CIRCUIT 9 117 34 127 109 6 14 27 32 123 122 125 3 1 11 13 51 54 52 STPMODE# (PD3) NMI# RESET# AAIND# (PC4) TMIND# (PB7) DTRIND# (PD0) OHIND# (PE0) TXD# (PA2) RXD# (PA6) CTS# (PC1) DSR# (PC0) RLSD# (PC2) TM# (PC6) RI# (PC5) DTR# (PD4) RTS# (PD6) RXCLK# (P_PB01) TXCLK# (P_PA05) XTCLK # (P_GP00) 98 96 97 93 94 LINE_SEL (PE7) 23 47K +3.3V 47K +3.3V NC 47K +3.3V NC NC
NC NC NC
RESERVED (PA5)
31 29 21 17 28
5
VOICE# (PE1) HS_LCS (PE4)
16 19
VOICE# HS_LCS
DAA
LED INTERFACE
DSPKOUT PWRCLKP PWRCLKN DIB_DATAP DIB_DATAN
SPEAKER CIRCUIT
DIGITAL ISOLATION BARRIER (DIB)
SERIAL DTE INTERFACE
SERIAL DTE SYNCHRONOUS CLOCKS
IASLEEP (P_PF05) M_CLK (P_PB00) SR2CLK (P_PGP05) SA2CLK (P_PX05) SR3OUT SR3IN (P_PX01) SR2IO (P_PX06)
50 37 92 38 35 36 39
SLEEP M_CLKIN M_SCK M_STROBE M_TXSIN M_RXOUT M_CNTRLSIN
CX20442 VOICE CODEC (VC) (OPTIONAL)
NC
24 22 26 110 121 45 126 7 8 46 101 4 12 55 56 59 41 42 43 60 2 15 40 58 78 100 108 116 124 20 53 85 10 25 30 44 48 68 90 95 103 112 120 128
RESERVED (PA0) RESERVED (PE6) RESERVED (PA1) TESTP PHS2 SR4IN PC3 PD1 PD2 PD7 RESERVED (PB1) RESERVED (PC7) RESERVED (PD5) RESERVED (P_PA00) RESERVED (P_PA05) RESERVED (BD2CLK) P_PX00 P_PX02 P_PX03 VGG VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD_CORE VDD_CORE VDD_CORE GND GND GND GND GND GND GND GND GND GND GND GND
CX81801 Smart Modem 128-Pin TQFP Serial Interface (PARIF = Low)
NVMCLK (PA7) NVMDATA (PE3)
33 18
EEPROM (OPTIONAL)
+3.3V or +5V
+3.3V
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 (PB0) A17 (PB4) A18 (PB5) D0 D1 D2 D3 D4 D5 D6 D7 WRITE# READ# ROMSEL# (PB2) RAMSEL# (PB3) EXT_RES# (PB6) PLLVDD
71 72 73 74 75 76 77 79 80 81 84 86 87 88 89 91 99 105 106 62 63 64 65 66 67 69 70 118 119 102 104 107 82 0.1 uF NC
EXTERNAL MEMORY
+3.3V
PLLGND
83
102199_005
3-12
Conexant
102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet
Figure 3-4. CX81801 Modem 128-Pin TQFP Pin Signals for Serial Interface (PARIF = Low)
GND AAIND# (PC4) PC3 RLSD# (PC2) VDD CTS# (PC1) DSR# (PC0) PHS2 GND READ# WRITE# NMI# VDD XTLO XTLI CLKIN GND DV1TP TESTP TMIND# (PB7) VDD EXT_RES# (PB6) A18 (PB5) A17 (PB4) RAMSEL# (PB3) GND 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
RI# (PC5) VDD TM# (PC6) RESERVED (PC7) PARIF DTRIND# (PD0) PD1 PD2 STPMODE# (PD3) GND DTR# (PD4) RESERVED (PD5) RTS# (PD6) OHIND# (PE0) VDD VOICE# (PE1) RESERVED (PE2) NVMDATA (PE3) HS_LCS (PE4) VDD_CORE RESERVED (PE5) RESERVED (PE6) LINE_SEL (PE7) RESERVED (PA0) GND RESERVED (PA1) TXD# (PA2) RESERVED (PA3) RESERVED (PA4) GND RESERVED (PA5) RXD# (PA6) NVMCLK (PA7) RESET# SR3OUT SR3IN (P_PX01) M_CLK (P_PB00) SA2CLK (P_PX05)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
ROMSEL# (PB2) RESERVED (PB1) VDD A16 (PB0) DSPKOUT PWRCLKN PWRCLKP GND DIB_DATAN DIB_DATAP SR2CLK (P_PGP05) A15 GND A14 A13 A12 A11 VDD_CORE A10 PLLGND PLLVDD A9 A8 A7 VDD A6 A5 A4 A3 A2 A1 A0 D7 D6 GND D5 D4 D3
CX81801 Serial Interface (PARIF Pin = Low)
VDD P_PX00 P_PX02 P_PX03 GND SR4IN PD7 NOXYCK GND XCLK IASLEEP (P_PF05) RXCLK# (P_PB01) XTCLK# (GP00) VDD_CORE TXCLK# (P_PA04) RESERVED (P_PA00) RESERVED (P_PA05) LPO VDD RESERVED (BD2CLK) VGG CLKOUT D0 D1 D2
SR2IO (P_PX06)
102199_006
102199B
Conexant
3-13
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-3. CX81801 Modem 128-Pin TQFP Pin Signals for Serial Interface (PARIF = Low)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Signal Label RI# (PC5) VDD TM# (PC6) RESERVED (PC7) PARIF DTRIND# (PD0) PD1 PD2 STPMODE# (PD3) GND DTR# (PD4) RESERVED (PD5) RTS# (PD6) OHIND# (PE0) VDD VOICE# (PE1) RESERVED (PE2) NVMDATA (PE3) HS_LCS (PE4) VDD_CORE RESERVED (PE5) SSD_RING# (PE6) LINE_SEL (PE7) RESERVED (PA0) GND SSD_INT (PA1) TXD# (PA2) RESERVED (PA3) RESERVED (PA4) GND RESERVED (PA5) RXD# (PA6) O P O I I O I/O I/O I G I I I O P O O I/O I P I/O O I O G O I I I G I O I/O I/O Type Ith/Ot8 PWR Ith/Ot8 Ith/Ot8 Itpu Ithpd/Ot2 Ithpd/Ot2 Ithpd/Ot2 Ith/Ot2 GND It Ithpu Ithpu It/Ot8 PWR It/Ot2 It/Ot2 It/Ot2 It/Ot2 PWR It/Ot2 It/Ot2 It/Ot8 It/Ot2 GND It/Ot2 It/Ot2 Itpu/Ot2 Itpu/Ot2 GND It/Ot2 It/Ot2 +3.3V DTE IF: TM# +3.3V through 47 K GND (serial interface) LED: DTRIND# NC NC NC GND DTE IF: DTR# NC DTE IF: RTS# LED: OHIND# +3.3V DAA: VOICE# NC NVRAM: SDA GND through 47 K Internal core voltage +3.3V through 47 K NC +3.3V through 47 K NC GND NC DTE IF: TXD# NC NC GND +3.3V through 47 K DTE IF: RXD# Interface DTE IF: RI# Pin 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 D3 D4 D5 GND D6 D7 A0 A1 A2 A3 A4 A5 A6 VDD A7 A8 A9 PLLVDD PLLGND A10 VDD_CORE A11 A12 A13 A14 GND A15 SR2CLK (P_PGP05) DIB_DATAP DIB_DATAN GND PWRCLKP Signal Label I/O I/O I/O I/O G I/O I/O O O O O O O O P O O O P G O P O O O O G O I I/O I/O G O I/O Type Ith/Ot2 Ith/Ot2 Ith/Ot2 GND Ith/Ot2 Ith/Ot2 It/Ot8 It/Ot8 It/Ot8 It/Ot8 It/Ot8 It/Ot8 It/Ot8 PWR It/Ot8 It/Ot8 It/Ot8 PWR GND It/Ot8 PWR It/Ot8 It/Ot8 It/Ot8 It/Ot8 GND It/Ot8 Itpu/Ot2 Idd/Odd Idd/Odd GND Odpc Interface EB: D3 EB: D4 EB: D5 GND EB: D6 EB: D7 EB: A0 EB: A1 EB: A2 EB: A3 EB: A4 EB: A5 EB: A6 +3.3V EB: A7 EB: A8 EB: A9 +3.3V and GND through 0.1 F GND EB: A10 Internal core voltage EB: A11 EB: A12 EB: A13 EB: A14 GND EB: A15 VC: M_SCK DIB: Data Pos. Channel DIB: Data Neg. Channel GND DIB: Transformer primary winding nondotted terminal DIB: Transformer primary winding dotted terminal Speaker Circuit EB: A16 +3.3V NC EB: ROM CE# GND EB: RAM CS# EB: A17 EB: A18 NC +3.3V LED: TMIND# NC
33
NVMCLK (PA7)
O
It/Ot2
NVRAM: SCL
97
PWRCLKN
O
Odpc
34 35 36 37 38 39 40 41 42 43 44 45 46
RESET# SR3OUT SR3IN (P_PX01) M_CLK (P_PB00) SA2CLK (P_PX05) SR2IO (P_PX06) VDD P_PX00 P_PX02 P_PX03 GND SR4IN PD7
I O I O I O P I/O I/O I/O G I I/O
It Ot2 Itk/Ot2 It/Ot2 Itpu/Ot2 It/Ot2 PWR It/Ot8 Itpu/Ot2 Itpu/Ot2 GND Itk It/Ot2
Reset Circuit VC: M_TXSIN VC: M_RXOUT VC: M_CLKIN VC: M_STROBE VC: M_CNTRLSIN +3.3V NC NC NC GND NC NC
98 99 100 101 102 103 104 105 106 107 108 109 110
DSPKOUT A16 (PB0) VDD RESERVED (PB1) ROMSEL# (PB2) GND RAMSEL# (PB3) A17 (PB4) A18 (PB5) EXT_RES# (PB6) VDD TMIND# (PB7) TESTP
O O P O O G O O O O P O I
It/Ot2 It/Ot2 PWR It/Ot2 Ot2 GND It/Ot2 It/Ot2 It/Ot2 It/Ot2 PWR It/Ot8 Itpu
3-14
Conexant
102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet Table 3-3. CX81801 Modem 128-Pin TQFP Pin Signals for Serial Interface (PARIF = Low) (Continued)
Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Signal Label NOXYCK GND XCLK IASLEEP (P_PF05) RXCLK# (P_PB01) XTCLK# (GP00) VDD_CORE TXCLK# (P_PA04) RESERVED (P_PA00) RESERVED (P_PA05) LPO VDD RESERVED (BD2CLK) VGG CLKOUT D0 D1 D2 I G O O O I P O I/O I/O I P O P O I/O I/O I/O I/O I/O Type Itpu GND It/Ot2 Ot2 Itpu/Ot2 It/Ot2 PWR Itpu/Ot2 Itpu/Ot2 Itk/Ot2 Itpu/Ot2 PWR Itpu/Ot2 PWRG It/Ot2 Ith/Ot2 IthOt2 Ith/Ot2 GND GND NC VC: SLEEP DTE: RXCLK DTE: XTCLK Internal core voltage DTE: TXCLK NC NC +3.3V through 240 K +3.3V NC +3.3V or +5V NC EB: D0 EB: D1 EB: D2 Interface Pin 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Signal Label DV1TP GND CLKIN XTLI XTLO VDD NMI# WRITE# READ# GND PHS2 DSR# (PC0) CTS# (PC1) VDD RLSD# (PC2) PC3 AAIND# (PC4) GND I G I I O P I O O G O I/O I/O P I/O I/O O G I/O I/O Type Itpu GND It Ix Ox PWR Ithpu It/Ot2 It/Ot2 GND Ot2 Ith/Ot8 Ith/Ot8 PWR Ith/Ot8 Ith/Ot8 Ith/Ot8 GND GND GND Crystal Circuit Crystal Circuit +3.3V +3.3V EB: WRITE# EB: READ# GND NC DTE IF: DSR# DTE IF: CTS# +3.3V DTE IF: RLSD# NC LED: AAIND# GND Interface Clock Select
Notes: 1. I/O Types: See Table 3-5. 2. Interface Legend: DIB Digital Isolation Barrier EB Expansion Bus HB Host Bus NC No internal pin connection VC Voice Codec
102199B
Conexant
3-15
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low)
Label XTLI, XTLO 114, 115 Pin I/O I, O I/O Type System Ix, Ox Crystal In and Crystal Out. If an external 28.224 MHz crystal circuit is used instead of an external clock circuit, connect XTLI and XTLO to the external crystal circuit and connect CLKIN to digital ground (GND). Clock In. If an external 28.224 MHz clock circuit is used instead of an external crystal circuit, connect CLKIN to the clock output and leave XTLI and XTLO open. Clock Out. 28.224 MHz output clock. Leave open. Clock Input Select. This input is used to choose the clock input. Connect to +3.3V or leave open to select XTLI as the clock input. Connect to GND to select CLKIN as the clock input. Parallel/Serial Interface Select. PARIF input high (open) selects parallel host interface operation (see signal definitions in Table 3-2); PARIF low (GND) selects serial DTE interface operation (see signal definitions in this table). Line Interface Select. Selects telephone line interface. Connect to +3.3V. Stop Mode. Not used. Leave open. Non-Maskable Interrupt. Not used. Connect to +3.3V. Reset. The active low RESET# input resets the Smart Modem logic, and restores the saved configuration from serial EEPROM or returns the modem to the factory default values if NVRAM is not present. RESET# low holds the modem in the reset state; RESET# going high releases the modem from the reset state. After application of VDD, RESET# must be held low for at least 15 ms after the VDD power reaches operating range. The modem device set is ready to use 25 ms after the low-to-high transition of RESET#. For serial Interface, the RESET# input is typically connected to a reset switch circuit. VGG VDD 60 2, 15, 40, 58, 78, 100, 108, 116, 124 20, 53, 85 10, 25, 30, 44, 48, 68, 90, 95, 103, 112, 120, 128 57 47 P P PWRG PWR I/O Signaling Voltage Source. Connect to +3.3V for +3.3V inputs, or to +5V for +5V inputs. Digital Supply Voltage. Connect to VCC (+3.3V, filtered). Signal Name/Description
CLKIN
113
I
It
CLKOUT DV1TP
61 111
O I
It/Ot2 Itpu
PARIF
5
I
Itpu
LINE_SEL (PE7) STPMODE# (PD3) NMI# RESET#
23 9 117 34
I I I I
It/Ot8 Ith/Ot2 Ithpu It
VDD_CORE GND
P G
PWR GND
Core Voltage. Internal core voltage. Digital Ground. Connect to digital ground (GND).
LPO NOXYCK
I I
I/O Itpu
Low Power Oscillator. Connect to +3.3V through 240 K. Disable XCLK Output. When low, disables XCLK output (reduces internal power consumption). When high, enables XCLK output. Connect to GND. PLL Circuit Digital Supply Voltage. Connect to +3.3V and to GND through 0.1 F.
PLLVDD PLLGND NVMCLK (PA7) NVMDATA (PE3)
82 83 33 18
P G O I/O
PWR
GND PLL Circuit Digital Ground. Connect to GND. Serial EEPROM (NVRAM) Interface It/Ot2 It/Ot2 NVRAM Clock. NVMCLK output high enables the EEPROM. Connect to EEPROM SCL pin. NVRAM Data. The NVMDATA pin supplies a serial data interface to the EEPROM. Connect to EEPROM SDA pin and to +3.3V through 10 K.
3-16
Conexant
102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low) (Continued)
Label DSPKOUT 98 Pin I/O O I/O Type Speaker Interface It/Ot2 Signal Name/Description
Modem Speaker Digital Output. The DSPKOUT digital output reflects the received analog input signal digitized to TTL high or low level by an internal comparator. DIB Interface Clock and Power Positive. Provides clock and power to the LSD. Connect to DIB transformer primary winding non-dotted terminal. Clock and Power Negative. Provides clock and power to the LSD. Connect to DIB transformer primary winding dotted terminal. Data Positive. Transfers data, control, and status information between the Smart Modem and the LSD. Connect to LSD through DIB data positive channel components.
PWRCLKP PWRCLKN DIB_DATAP
96 97 93
O O I/O
Odpc Odpc Idd/Odd
DIB_DATAN
94
I/0
Idd/Odd
Data Negative. Transfers data, control, and status information between the Smart Modem and the LSD. Connect to LSD through DIB data negative channel components. External Bus Interface Address Lines 0-18. A0-A18 are the address output lines used to access external memory; up to 4 Mb (512 KB) ROM/flash ROM using A0-A18 and up to 1 Mb (128 KB) RAM using A0-A16. The 256 KB base modem ROM code is located in the 0-256 KB address range. Data Line 0-7. D0-D7 are bidirectional external memory bus data lines. Read Enable. READ# output low enables data transfer from the selected device to the D0-D7 lines. Write Enable. WRITE# output low enables data transfer from the D0-D7 lines to the selected device. ROM Select. ROMSEL# (PB2, ES3) output low selects the external ROM. RAM Select. RAMSEL# (PB3, ES2) output low selects the external RAM. Reserved. PB1 (ES4) is used internally. Leave open.
A0-A9, A10-A15, A16 (PB0), A17 (PB4), A18 (PB5) D0-D7 READ# WRITE# ROMSEL# (PB2) RAMSEL# (PB3) RESERVED (PB1) EXT_RES# (PB6)
71-77, 79-81, 84, 86-89, 91, 99, 105, 106 62-67, 69-70 119 118 102 104 101 107
O, O, O, O, O I/O O O O O O O
It/Ot8, It/Ot8, It/Ot2, It/Ot2, It/Ot2 Ith/Ot2 It/Ot2 It/Ot2 Ot2 It/Ot2 It/Ot2 It/Ot2
External Device Reset. Active low reset for external devices. Leave open if not used. CX20442 VC Interface Modem Sleep. Connect to VC SLEEP pin. Master Clock Output. Connect to VC M_CLKIN pin. Voice Serial Clock input. Connect to VC M_SCK pin. Voice Serial Frame Sync Input. Connect to VC M_STROBE pin. Voice Serial Transmit Data Output. Connect to VC M_TXSIN pin. Voice Serial Receive Data Input. Connect to VC M_RXOUT pin. Voice Control Output. Connect to VC M_CNTRLSIN pin.
IASLEEP (P_PF05) M_CLK (P_PB00) SR2CLK (P_PGP05) SA2CLK (P_PX05) SR3OUT SR3IN (P_PX01) SR2IO (P_PX06)
50 37 92 38 35 36 39
O O I I O I O
Ot2 It/Ot2 Itpu/Ot2 Itpu/Ot2 Ot2 Itk/Ot2 It/Ot2
102199B
Conexant
3-17
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low) (Continued)
Label TXD# (PA2) 27 Pin I/O I/O Type Signal Name/Description V.24 (EIA/TIA-232-E) DTE Serial Interface I It/Ot2 Transmitted Data (EIA BA/ITU-T CT103). The DTE uses the TXD# line to send data to the modem for transmission over the telephone line or to transmit commands to the modem. Received Data (EIA BB/ITU-T CT104). The modem uses the RXD# line to send data received from the telephone line to the DTE and to send modem responses to the DTE. During command mode, RXD# data represents the modem responses to the DTE. Clear To Send (EIA CB/ITU-T CT106). CTS# output ON (low) indicates that the modem is ready to accept data from the DTE. In asynchronous operation, in error correction or normal mode, CTS# is always ON (low) unless RTS/CTS flow control is selected by the &Kn command. In synchronous operation, the modem also holds CTS# ON during asynchronous command state. The modem turns CTS# OFF immediately upon going off-hook and holds CTS# OFF until both DSR# and RLSD# are ON and the modem is ready to transmit and receive synchronous data. The modem can also be commanded by the &Rn command to turn CTS# ON in response to an RTS# OFF-to-ON transition. DSR# (PC0) 122 O Ith/Ot8 Data Set Ready (EIA CC/ITU-T CT107). DSR# indicates modem status to the DTE. DSR# OFF (high) indicates that the DTE is to disregard all signals appearing on the interchange circuits except Ring Indicator (RI#). DSR# output is controlled by the AT&Sn command. Received Line Signal Detector (EIA CF/ITU-T CT109). When AT&C0 command is not in effect, RLSD# output is ON when a carrier is detected on the telephone line or OFF when carrier is not detected. Test Mode (EIA TM/ITU-T CT142). The TM# output indicates the modem is in test mode (low) or in any other mode (high). Ring Indicator (EIA CE/ITU-T CT125). RI# output ON (low) indicates the presence of an ON segment of a ring signal on the telephone line. Data Terminal Ready (EIA CD/ITU-T CT108). The DTR# input is turned ON (low) by the DTE when the DTE is ready to transmit or receive data. DTR# ON prepares the modem to be connected to the telephone line, and maintains the connection established by the DTE (manual answering) or internally (automatic answering). DTR# OFF places the modem in the disconnect state under control of the &Dn and &Qn commands. Request To Send (EIA CA/ITU-T CT105). RTS# input ON (low) indicates that the DTE is ready to send data to the modem. In the command state, the modem ignores RTS#. In asynchronous operation, the modem ignores RTS# unless RTS/CTS flow control is selected by the &Kn command. In synchronous on-line operation, the modem can be commanded by the &Rn command to ignore RTS# or to respond to RTS# by turning on CTS# after the delay specified by Register S26.
RXD# (PA6)
32
O
It/Ot2
CTS# (PC1)
123
O
Ith/Ot8
RLSD# (PC2)
125
O
Ith/Ot8
TM# (PC6) RI# (PC5)
3 1
O O
Ith/Ot8 Ith/Ot8
DTR# (PD4)
11
I
It
RTS# (PD6)
13
I
Ithpu
3-18
Conexant
102199B
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low) (Continued)
Label RXCLK# (P_PB01) 51 Pin I/O I/O Type Signal Name/Description V.24 (EIA/TIA-232-E) DTE Serial Interface (Continued) O Itpu/Ot2 Receive Data Clock. A synchronous Receive Data Clock (RXCLK) is output in synchronous modes. The RXCLK frequency is the data rate (0.01%) with a duty cycle of 501%. Leave open if not used. Transmit Data Clock. A synchronous Transmit Data Clock (TXCLK) is output in synchronous modes. The TXCLK frequency is the data rate (0.01%) with a duty cycle of 501%. Leave open if not used.
TXCLK# (P_PA04)
54
O
Itpu/Ot2
XTCLK# (GP00)
52
I
It/Ot2
External Data Clock. A synchronous External Transmit Data Clock (XTCLK) is input in synchronous modes. LED Indicator Interface Auto Answer Indicator. AAIND# output ON (low) corresponds to the indicator on. AAIND# output is active when the modem is configured to answer the ring automatically (ATS0 command 0). Test Mode Indicator. TMIND# output ON (low) corresponds to the indicator on. TMIND# output pulses (indicator flashes) when the modem is in test mode and if an error is detected. DTR Indicator. DTRIND# output ON (low) corresponds to the indicator on. The DTRIND# state reflects the DTR# output state except when the &D0 command is active, in which case DTRIND# is low. Off-Hook Indicator. OHIND# (PE0) indicates the status of the offhook relay.
AAIND# (PC4)
127
O
Ith/Ot8
TMIND# (PB7)
109
O
It/Ot8
DTRIND# (PD0)
6
O
Ithpd/Ot2
OHIND# (PE0)
14
O
It/Ot8
102199B
Conexant
3-19
CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-4. CX81801 Modem Pin Signal Definitions for Serial Interface (PARIF = Low) (Continued)
Label VOICE# (PE1) HS_LCS (PE4) 16 19 Pin I/O O I I/O Type DAA Interface It/Ot2 It/Ot2 Signal Name/Description
Voice Relay Control. This output (typically active low) used to control the normally open voice relay. Handset Line Current Sense. LCS is an active high input that indicates a handset off-hook status. Not required for data/fax/voice/speakerphone operation. If not used, connect to GND through 47 K. Not Used Test. Used for factory test only. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Reserved. Connect to +3.3V though 47 K. Reserved. Connect to +3.3V through 47 K. Reserved. Leave open. Not Used. Leave open. Reserved. Connect to +3.3V though 47 K. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open.
TESTP XCLK S4RIN PHS2 PC3 PD1 PD2 PD7 P_PX00 P_PX02 P_PX03 RESERVED (PA0) RESERVED (PA1) RESERVED (PA3) RESERVED (PA4) RESERVED (PA5) RESERVED (PC7) RESERVED (PD5) RESERVED (PE2) RESERVED (PE5) RESERVED (PE6) RESERVED (P_PA00) RESERVED (P_PA05)
110 49 45 121 126 7 8 46 41 42 43 24 26 28 29 31 4 12 17 21 22 55 56
I O I O I/O I/O I/O I/O I/O I/O I/O O O I I I I I O I/O O I/O I/O
Itpu It/Ot2 Itk Ot2 Ith/Ot8 Ithpd/Ot2 Ithpd/Ot2 It/Ot2 It/Ot8 Itpu/Ot2 Itpu/Ot2 It/Ot2 It/Ot2 Itpu/Ot2 Itpu/Ot2 It/Ot2 Ith/Ot8 Ithpu It/Ot2 It/Ot2 It/Ot2 Itpu/Ot2 Itk/Ot2
RESERVED 59 I/O Itpu/Ot2 Not Used. Leave open. (P_BD2CLK) Notes: 1. I/O Types: See Table 3-5. 2. Interface Legend: DIB Digital Isolation Barrier EB Expansion Bus HB Host Bus NC No internal pin connection VC Voice Codec RESERVED = No external connection allowed (may have internal connection).
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Table 3-5. CX81801 Modem I/O Type Definitions
I/O Type Idd/Odd Ix/Ox It/Ot2 Itk/Ot2 Itpu/Ot2 It/Ot8 Ithpd/Ot2 Ith/Ot2 Ith/Ot8 It Itk Itkpu Itpu Ithpu Odpc Ot2 Description Digital input/output, DIB data transceiver I/O, wire Digital input, +5V tolerant/ Digital output, 2 mA, ZINT = 120 Digital input, +5V tolerant, keeper/ Digital output, 2 mA, ZINT = 120 Digital input, +5V tolerant, 75k pull up/ Digital output, 2 mA, ZINT = 120 Digital input, +5V tolerant,/ Digital output, 8 mA, ZINT = 50 Digital input, +5V tolerant, hysteresis, 75k pull down/ Digital output, 2 mA, ZINT = 120 Digital input, +5V tolerant, hysteresis/Digital output, 2 mA, ZINT = 120 Digital input, +5V tolerant, hysteresis/Digital output, 8 mA, ZINT = 50 Digital input, +5V tolerant Digital input, +5V tolerant, keeper Digital input, +5V tolerant, keeper, 75k pull up Digital input, +5V tolerant, 75k pull up Digital input, +5V tolerant, hysteresis, 75k pull up Digital output with adjustable drive, DIB clock and power
Digital output, three-state, 2 mA, ZINT = 120 PWR VCC Power PWRG VGG Power GND Ground NOTES: 1. See DC characteristics in Table 3-6. 2. I/O Type corresponds to the device Pad Type. The I/O column in signal interface tables refers to signal I/O direction used in the application.
Table 3-6. CX81801 Modem DC Electrical Characteristics
Parameter Input Voltage Low +5V tolerant +5V tolerant hysteresis Input Voltage High +5V tolerant +5V tolerant hysteresis Input Hysteresis +3V hysteresis +5V tolerant, hysteresis Output Voltage Low ZINT = 120 ZINT = 50 Output Voltage High ZINT = 120 ZINT = 50 Pull-Up Resistance Pull-Down Resistance Rpu Rpd VOH 2.4 2.4 50 50 Symbol VIL 0 0 VIH 2 0.7 * VDD VH 0.5 0.3 VOL 0 0 - - - - - - - 0.4 0.4 VDD VDD 200 200 V V V V V k IOL = 2 mA IOL = 8 mA IOL = -2 mA IOL = -8 mA - - - - - - - - 0.8 0.3 * VGG 5.25 5.25 V V V V V V V V Min. Typ. Max. Units Test Conditions
k Test Conditions unless otherwise stated: VDD = +3.3 0.3 VDC; TA = 0C to 70C; external load = 50 pF.
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3.2
3.2.1
3.2.1.1
CX20493 LSD Hardware Pins and Signals
CX20493 LSD Signal Summary
Smart Modem Interface (Through DIB)
The DIB interface, power, and ground signals are: * * * * * * * * Clock (CLK, pin 26); input Digital Power (PWR+, pin 7); unregulated input power Regulated Digital Voltage Supply (DVdd, pin 24) Digital Ground (DGnd, pin 23); digital ground Regulated Analog Voltage Supply (AVdd, pin 2) Analog Ground (AGnd, pin 6); analog ground Data Positive (DIB_P, pin 27); input/output Data Negative (DIB_N, pin 28); input/output
3.2.1.2
Telephone Line Interface
The telephone line interface signals are: * * * * * * * * * * * * * RING 1 AC Coupled (RAC1, pin 21); input TIP 1 AC Coupled (TAC1, pin 20); input RING 2 AC Coupled (RAC2, pin 19); input TIP 2 AC Coupled (TAC2, pin 18); input TIP and RING DC Measurement (TRDC, pin 12); input Electronic Inductor Capacitor (EIC, pin 11) Electronic Inductor Output (EIO, pin 17) Electronic Inductor Feedback (EIF, pin 16) Receive Analog Input (RXI, pin 9); input Transmit Output (TXO, pin 14); output Transmit Feedback (TXF, pin 13); input Virtual Impedance 0 (VZ, pin 10); input Electronic Inductor Ground (DC_GND, pin 15)
3.2.1.3
Voltage References
There are three reference voltage pins: * * * Output Middle (Center) Reference Voltage (Vc, pin 3); output for decoupling Output Reference Voltage (VRef, pin 4); output for decoupling Bias Resistor (RBias, pin 5); input
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3.2.1.4
General Purpose Input/Output
There is one unassigned general purpose input/output pin: * General Purpose Input/Output 1 (GPIO1, pin 1); input/output
3.2.1.5
No Connects
Three pins are not used: * * * No Connect 1 (NC1, pin 8); no internal connection No Connect 2 (NC2, pin 22); no internal connection No Connect 3 (NC3, pin 25); no internal connection
3.2.2
CX20493 LSD Pin Assignments and Signal Definitions
CX20493 LSD hardware interface signals are shown by major interface in Figure 3-5, are shown by pin number in Figure 3-6, and are listed by pin number in Table 3-7. CX20493 LSD hardware interface signals are defined in Table 3-8. CX20493 LSD GPIO DC electrical characteristics are specified in Table 3-9. CX20493 LSD AVdd DC electrical characteristics are listed in Table 3-10.
Figure 3-5. CX20493 LSD Hardware Interface Signals
RAC2 TAC2 19 18
On-hook Monitor (Optional) Ring Filter Electronic Inductor, Off-Hook, Pulse Dial, and TIP and RING VI Control
Vdd C978
24
DVdd
RAC1 TAC1
21 20
DGND_LSD
EIC TRDC EIO EIF
11 12 17 16
DIGITAL ISOLATION BARRIER (DIB)
C950 BR908 CC
PCLK2
R932 CLK2
C926 26 FB906 7 PWR+ CLK RXI 9
Safety and EMI Protection
Telephone Line Connector
TIP RING
R950 PWRCLKN
POWER AND CLOCK CHANNEL
BR908 AC1 R990
Vdd 2 AVdd
C962 R952 PWRCLKP R922
+
BR908
-
C970
C930
C928 6 AGnd
CX20493 SmartDAA 3 Line Side Device (LSD) 28-Pin QFN
Receive Coupling
AGND_LSD
VZ TXO TXF
10 14 13
Impedance Matching and Transmitter
R954
RBias AGND_LSD 27 VRef DIB_P Vc DIB_N
5
C952
DATA CHANNEL
AGND_LSD 4
R924 DIB_DATAP R926 DIB_DATAN C924 C922
3 C944 C974 C940 C976
28
29 15
PADDLE DC_GND DGND GPIO1 NC1 NC2 NC3 1 8 22 25 AGND_LSD NC NC NC NC
NOTE: Consult applicable reference design for exact component placement and values, and for layout guidelines.
AGND_LSD GND_TIE U908
23
AGND_LSD
DGND_LSD
101701_006
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Figure 3-6. CX20493 LSD 28-Pin QFN Pin Signals
DIB_N
DIB_P
DGnd 23
DVdd
NC3
28
27
26
25
24
22
NC2
CLK
GPIO1 AVdd Vc Vref RBias AGnd PWR+
1 2 3 4 5 6 7 8 9 13 10 11 12 14
21 20 19 18 17
RAC1 TAC1 RAC2 TAC2 EIO EIF DC_GND
CX20493
16 15
NC1
TRDC
RXI
VZ
EIC
TXO
TXF
101701A_007
Table 3-7. CX20493 LSD 28-Pin QFN Pin Signals
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GPIO1 AVdd Vc VRef RBias AGnd PWR+ NC1 RXI VZ EIC TRDC TXF TXO Signal Label 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin DC_GND EIF EIO TAC2 RAC2 TAC1 RAC1 NC2 DGnd DVdd NC3 CLK DIB_P DIB_N Signal Label
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Table 3-8. CX20493 LSD Hardware Signal Definitions
Label AVdd Pin 2 I/O PWR I/O Type PWR Signal Name/Description System Signals Regulated Power Output. Provides external power for LSD digital circuits and a connection point for external decoupling. (AVdd is routed internally to LSD analog circuits.) See PWR+ pin description. Connect to LSD DVdd pin and connect to AGND_LSD through C928 and C930 in parallel. C928 and C930 must be placed close to pins 2 and 6. C930 must have ESR < 2 . Analog Ground. Connect to minus (-) terminal of full wave rectifier (FWR). Connect FWR BR980 terminal to DIB transformer secondary winding undotted terminal through R922. Output Reference Voltage. Connect to AGND_LSD through C940 and C976, which must be placed close to pin 4. Ensure a very close proximity between C940 and the VRef pin. C940 must have a maximum ESR of 2 . Output Reference Voltage. Connect to AGND_LSD through C940 and C976, which must be placed close to pin 4. Ensure a very close proximity between C940 and the VRef pin. C940 must have a maximum ESR of 2 . Output Middle Reference Voltage. Connect to AGND_LSD through C944 and C974, which must be placed close to pin 3. Ensure a very close proximity between C944 and the Vc pin. Use a short path and a wide trace to AGND_LSD pin. Unregulated Power Input. Provides unregulated input power to the LSD. PWR+ pin is an input which takes unregulated +3.2V to +4.5V from the DIB power supply made up of the transformer, full-wave rectifier, and filter capacitors. The PWR+ input is regulated by an internal linear regulator to +3.3V 5% which is routed to the AVdd pin. If PWR+ is less than +3.4V, then AVdd is equal to the unregulated PWR+ input value minus 150 mV (Table 3-10). Connect to plus (+) terminal of FWR. Connect terminal BR908 AC1 to DIB transformer secondary winding dotted terminal through R990. Connect transformer side of FB906 to AGND_LSD though C970. Place FB906 and C970 close to pin 7 and pin 6 (AGnd). Digital Power Input. Input power for LSD digital circuits. Connect to LSD AVdd pin and connect to DGND_LSD through C978. Place C978 near pin 24. LSD Digital Ground. Connect to DGND_LSD, and to AGND_LSD at the DGND_LSD/AGND_LSD tie point (U908). Paddle Ground. Referred to as pin 29 in schematics. Connect to AGND_LSD. DIB Interface Signals Clock. Provides input clock, AC coupled to the LSD. Connect to DIB transformer secondary winding undotted terminal through C926 (closest to the CX20493), R932, then R922 in series. Connect the R932 and R922 node to LSD AGND pin through full-wave rectifier BR908. Place C926 near pin 26 and place R932 near C926. Data and Control Positive. Connect to DIBDAT_P through R924 in series with C922. DIB_P and DIB_N signals are differential and halfduplex bidirectional. Data and Control Negative. Connect to DIBDAT_N through R926 in series with C924. DIB_P and DIB_N signals are differential and halfduplex bidirectional.
AGnd
6
AGND_LSD
AGND_LSD
VRef
4
REF
REF
VRef
4
REF
REF
Vc
3
REF
REF
PWR+
7
PWR
PWR
DVdd
24
PWR
PWR
DGnd PADDLE
23 --
DGND_LSD AGND_LSD
DGND_LSD AGND_LSD
CLK
26
I
I
DIB_P
27
I/O
I/O
DIB_N
28
I/O
I/O
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Table 3-8. CX20493 LSD Hardware Signal Definitions (Continued)
Label RAC1 TAC1 Pin 21 20 I/O I I I/O Type Ia Ia Signal Name/Description TIP and RING Interface RING1 AC Coupled and TIP1 AC Coupled. AC-coupled voltage from telephone line used to detect ring. Connect RAC1 to the diode bridge AC node (RING) through R902 (connects to pin 21) and C902 in series. Connect TAC1 to the diode bridge AC node (TIP) through R904 (connects to pin 20) and C904 in series. RING2 AC Coupled and TIP2 AC Coupled. AC-coupled voltage from telephone line used to optionally detect signal while on-hook. Connect RAC2 to the diode bridge AC node (RING) through R948 (connects to pin 19) and C948. Leave open if not used. Connect TAC2 to the diode bridge AC node (TIP) through R946 (connects to pin 21) and C946. Leave open if not used. Electronic Inductor Capacitor Switch. Internally switched to TRDC when pulse dialing. Connect to AGND_LSD through C958. TIP and RING DC Measurement. Input on-hook voltage (from a resistive divider). Used internally to extract TIP and RING DC voltage and Line Polarity Reversal (LPR) information. R906 and C918 must be placed very close to pin 12. Electronic Inductor Output. Calculated voltage is applied to this output to control off-hook and DC VI mask operation. Connect to base of Q902. LSD Electronic Inductor Ground. Connect to AGND_LSD and to the GND_LSD/AGND_LSD tie point (U908). Electronic Inductor Feedback. Connect to emitter of Q904 through R968. Receive Analog Input. Receiver operational amplifier inverting input. AC coupled to the Bridge CC node through R910 (connects to pin 9) and C912 in series. R910 and C912 must be placed very close to pin 9. The length of the PCB trace connecting R910 to the RXI pin must be kept at an absolute minimum. Receiver Bias. Connect to AGND_LSD through R954, which must be placed close to pin 5. Virtual Impedance. Input signal used to provide line complex impedance matching for worldwide countries. AC coupled to Bridge CC node through R908 (connects to pin 10) and C910 in series. R908 and C910 must be placed very close to pin 10. The length of the PCB trace connecting R908 to the VZ pin must be kept at an absolute minimum. Transmit Output. Outputs transmit signal and impedance matching signal; connect to base of transmitter transistor Q906. Transmit Feedback. Connect to emitter of transmitter transistor Q906. Not Used General Purpose I/O 1. Leave open if not used. No Connect. No internal connection. Leave open. No Connect. No internal connection. Leave open. No Connect. No internal connection. Leave open.
RAC2 TAC2
19 18
I I
Ia Ia
EIC TRDC
11 12
O I
Oa Ia
EIO DC_GND EIF RXI
17 15 16 9
O GND I I
Oa AGND_LSD Ia Ia
RBias VZ
5 10
I I
Ia Ia
TXO TXF
14 13
O I I/O
Oa Ia It/Ot12
GPIO1 1 NC1 8 NC2 22 NC3 25 Notes: 1. I/O types*: Ia It Oa Ot12
Analog input Digital input, TTL-compatible Analog output Digital output, TTL-compatible, 12 mA, ZINTERNAL = 32
AGND_LSD Isolated LSD Analog Ground GND_LSD Isolated LSD Digital Ground *See CX20493 LSD GPIO DC Electrical Characteristics (Error! Reference source not found.). 2. Refer to applicable reference design for exact component placement and values.
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Table 3-9. CX20493 LSD GPIO DC Electrical Characteristics
Parameter Input Voltage Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Symbol VIN VIL VIH VOL Min. -0.30 - 1.6 0 Typ. - - - - Max. 3.465 1.0 - 0.33 Units V V V V Test Conditions DVdd = +3.465V
VOH 2.97 - - V Input Leakage Current - -10 - 10 A Output Leakage Current (High Impedance) - -10 - 10 A GPIO Output Sink Current at 0.33 V maximum - 2.4 - mA GPIO Output Source Current at 2.97 V minimum - 2.4 - mA GPIO Rise Time/Fall Time 20 100 ns Test Conditions unless otherwise stated: DVdd = +3.3V +5%; TA = 0C to 70C; external load = 50 pF
Table 3-10. CX20493 AVdd DC Electrical Characteristics
PWR+ Input +3.4V < PWR+ < +4.5V AVdd Output +3.3V 5% +3.2V < PWR+ < +3.39V 3.05V < AVdd < 3.24V See PWR+, AVdd, and DVdd descriptions in Table 3-8.
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3.3
3.3.1
CX20442 VC Hardware Pins and Signals (S Models)
CX20442 VC Signal Summary
Microphone and analog speaker interface signals, as well as telephone handset/headset interface signals are provided to support functions such as speakerphone mode, telephone emulation, microphone voice record, speaker voice playback, and call progress monitor.
3.3.1.1
Speakerphone Interface
The following signals are supported: * * Speaker Out (M_SPKR_OUT); analog output - Should be used in speakerphone designs where sound quality is important Microphone (M_MIC_IN); analog input
3.3.1.2
Telephone Handset/Headset Interface
The following interface signals are supported: * * * Telephone Input (M_LINE_IN), input (TELIN) - Optional connection to a telephone handset interface circuit Telephone output (M_LINE_OUTP); output (TELOUT) - Optional connection to a telephone handset interface circuit Center Voltage (VC); output reference voltage
3.3.1.3
CX81801 Modem Interface
The following interface signals are supported: * * * * * * * Sleep (SLEEP); input Master Clock (M_CLKIN); input Serial Clock (M_SCK); output Control (M_CNTRLSIN); input Serial Frame Sync (M_STROBE); output Serial Transmit Data (M_TXSIN); input Serial Receive Data (M_RXOUT); output
3.3.1.4
Host Interface
The following interface signals are supported: * Reset (POR); input
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3.3.2
CX20442 VC Pin Assignments and Signal Definitions
VC 32-pin TQFP hardware interface signals are shown by major interface in Figure 3-7, are shown by pin number in Figure 3-8, and are listed by pin number in Table 3-11. VC hardware interface signals are defined in Table 3-12. VC pin signal DC electrical characteristics are defined in Table 3-13. VC pin signal analog electrical characteristics are defined in Table 3-14.
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Figure 3-7. CX20442 VC Hardware Interface Signals
CX81801
IASLEEP DRESET# M_CLK V_SCLK V_STROBE V_TXSIN V_RXOUT V_CTRL
1 4 19 21 23 20 22 18
M_DIG_SPEAKER SLEEP POR M_CLKIN M_SCK M_STROBE M_TXSIN M_RXOUT M_CNTRLSIN M_MIC_IN M_SPKR_OUT M_LINE_IN M_LINE_OUTP M_LINE_OUTM VREF
2 13 3 14 9 10 11 0.1uF 10uF
NC MIC SPKOUT TELIN TELOUT AUDIO CIRCUIT HANDSET INTERFACE
+3.3V
17 25 5 28 26
VDD VDD MAVDD VSS SET3V_BAR2
VAA (+3.3V)
CX20442 Voice Codec (VC) 32-Pin TQFP
AGND VC 12 0.1uF 10uF
GND 6 27 MAVSS VSUB M_MIC_BIAS M_RELAYA M_RELAYB M_ACT90 M_1BIT_OUT D_LPBK_BAR NC NC NC
AGND 15 24 16 29 30 31 7 8 32
AGND
NC
102199_009
Figure 3-8. CX20442 VC 32-Pin TQFP Pin Signals
NC D_LPBK_BAR M_1BIT_OUT M_ACT90 VSS VSUB SET3V_BAR2 VDD 32 31 30 29 28 27 26 25
SLEEP M_DIG_SPEAKER M_SPKR_OUT POR MAVDD MAVSS NC NC
1 2 3 4 5 6 7 8
24 23 22 21 20
M_RELAYA M_STROBE M_RXOUT M_SCK M_TXSIN M_CLKIN M_CNTRLSIN VDD
CX20442
9 10 11 12 13 14 15 16 M_LINE_OUTP M_LINE_OUTM VREF VC M_MIC_IN M_LINE_IN M_MIC_BIAS M_RELAYB
19 18 17
102199_010
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Table 3-11. CX20442 VC 32-Pin TQFP Pin Signals
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Signal Label SLEEP M_DIG_SPEAKER M_SPKR_OUT POR MAVDD MAVSS NC NC M_LINE_OUTP M_LINE_OUTM VREF VC M_MIC_IN M_LINE_IN M_MIC_BIAS M_RELAYB VDD M_CNTRLSIN M_CLKIN M_TXSIN M_SCK M_RXOUT M_STROBE M_RELAYA VDD M_SET3V_BAR2 VSUB VSS M_ACT90 M_1BIT_OUT D_LPBK_BAR NC P I I I O O O O P I G G I O I I I O O I O O I P G I/O CX81801: IASLEEP NC Speaker interface circuit Host: RESET# or reset circuit VAA (+3.3V) AGND NC NC Handset interface circuit: TELOUT NC AGND through capacitors AGND through capacitors Microphone interface circuit Handset interface circuit: TELIN NC NC +3.3V CX81801: V_CTRL CX81801: M_CLK CX81801: V_TXSIN CX81801: V_SCLK CX81801: V_RXOUT CX81801: V_STROBE NC +3.3V GND AGND GND NC NC NC NC Interface
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Table 3-12. CX20442 VC Pin Signal Definitions
Label VDD MAVDD VSS MAVSS VSUB POR SET3V_BAR2 SLEEP M_CLKIN M_SCK M_CNTRL_SIN M_STROBE M_TXSIN M_RXOUT M_MIC_IN M_SPKR_OUT Pin 17, 25 5 28 6 27 4 26 1 19 21 18 23 20 22 13 3 I/O P P G G G I I I I O I O I O I O I/O Type System Signals PWR PWR GND AGND GND Itpu Itpu Itpd Itpd Ot2 Itpd Ot2 Itpd Digital Power Supply. Connect to +3.3V and digital circuits power supply filter. Analog Power Supply. Connect to +3.3V and analog circuits power supply filter. Digital Ground. Connect to GND. Analog Ground. Connect to AGND. Analog Ground. Connect to AGND. Power-On Reset. Active low reset input. Connect to Host RESET# or reset circuit. Set +3.3V Analog Reference. Connect to GND. IA Sleep. Active high sleep input. Connect to CX81801 IASLEEP pin. Master Clock Input. Connect to CX81801 M_CLK pin. Serial Clock Output. Connect to CX81801 V_SCLK pin. Control Input. Connect to CX81801 V_CTRL pin. Serial Frame Sync. Connect to CX81801 V_STROBE pin. Serial Transmit Data. Connect to CX81801 V_TXSIN pin. Signal Name/Description
CX81801 Interconnect
Ot2 Serial Receive Data. Connect to CX81801 V_RXOUT pin. Microphone/Speaker Interface I(DA) O(DF) Microphone Input. Single-ended analog input from the microphone circuit.
Modem Speaker Analog Output. The M_SPKR_OUT analog output reflects the received analog input signal. The M_SPKR_OUT on/off and three levels of attenuation are controlled by bits in DSP RAM. When the speaker is turned off, the M_SPKR_OUT output is clamped to the voltage at the VC pin. The M_SPKR_OUT output can drive an impedance as low as 300 . In a typical application, the M_SPKR_OUT output is an input to an external LM386 audio power amplifier. Handset/Headset Interface Telephone Handset Out (TELOUT). Single-ended analog data output to the telephone handset circuit. The output can drive a 300 load. Telephone Handset Out (TELIN). Single-ended analog data input from the telephone handset circuit.
M_LINE_OUTP
9
O
O(DF)
M_LINE_IN
14
I
I(DA)
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Table 3-15. CX20442 VC Pin Signal Definitions (Continued)
Label VREF 11 Pin I/O R I/O Type Reference Voltage REF Signal Name/Description
High Voltage Reference. Connect to analog ground through 10 F (polarized, + terminal to VREF) and 0.1 F (ceramic) in parallel. Ensure a very close proximity between these capacitors and VREF pin. Low Voltage Reference. Connect to analog ground through 10 F (polarized, + terminal to VC) and 0.1 F (ceramic) in parallel. Ensure a very close proximity between these capacitors and VC pin. For handset interface, also connect to handset interface circuit (VC_HAND). Not Used
VC
12
R
REF
M_DIG_SPEAKER M_LINE_OUTM M_RELAYA M_RELAYB M_MIC_BIAS M_ACT90 M_1BIT_OUT D_LPBK_BAR NC Notes: 1. I/O types*: Ia It Itpd Itpu Oa Ot2 Ot2od AGND GND
2 10 24 16 15 29 30 31 7, 8, 32
O O O O O I O I
Ot2 Oa Ot Ot Oa Itpu Ot2 It
Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Not Used. Leave open. Internal No Connect. Leave open.
Analog input Digital input, TTL-compatible Digital input, TTL-compatible, internal 75k 25k pull-down Digital input, TTL-compatible, internal 75k 25k pull-up Analog output Digital output, TTL-compatible, 2 mA, ZINTERNAL = 120 Digital output, TTL-compatible, 2 mA, open drain, ZINTERNAL = 120 Analog Ground Digital Ground
Table 3-13. CX20442 VC DC Electrical Characteristics
Parameter Input Voltage Input Voltage Low Input Voltage High Output Voltage Low Output Voltage High Symbol VIN VIL VIH VOL Min. -0.30 -0.30 0.4*VDD 0 Typ. - - - - Max. VDD+0.3 0.2 *VDD VDD+0.3 0.4 Units V V V V Test Conditions
VOH 0.8*VDD - VDD V Input Leakage Current - -10 - 10 A Output Leakage Current (High - -10 - 10 A Impedance) Test Conditions unless otherwise stated: VDD = +3.3 0.3 VDC; TA = 0C to 70C; external load = 50 pF
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CX81801-7x/8x SmartV.XX Modem Data Sheet
Table 3-14. CX20442 VC Analog Electrical Characteristics
Signal Name M_LINE_IN, M_MIC_IN M_LINE_OUTP O (DD) Type I (DA) Characteristic Input Impedance AC Input Voltage Range Reference Voltage Minimum Load Maximum Capacitive Load Output Impedance AC Output Voltage Range Reference Voltage DC Offset Voltage Minimum Load Maximum Capacitive Load Output Impedance Value > 70K 1.1 VP-P +1.35 VDC 300 0 F 10 1.4 VP-P (with reference to ground and a 600 load) +1.35 VDC 200 mV 300 0.01 F
M_SPKR_OUT
O (DF)
10 AC Output Voltage Range 1.4 VP-P Reference Voltage +1.35 VDC DC Offset Voltage 20 mV Test Conditions unless otherwise stated: VDD = +3.3 0.3 VDC; MAVDD = +3.3 0.3 VDC, TA = 0C to 70C
Parameter DAC to Line Driver output (600 load, 3dB in SCF and CTF) SNR/SDR at: 4Vp-p differential 2Vp-p differential -10dBm differential DAC to Speaker Driver output (150 load, 3dB in SCF and CTF, -6dB in speaker driver) SNR/SDR at: 2Vp-p 1Vp-p -10dBm Line Input to ADC (6dB in AAF) SNR/SDR at -10 dBm Input Leakage Current (analog inputs) Output Leakage Current (analog outputs)
Min
Typ 88/85 82/95 72/100
Max
Units dB
dB 88/75 82/80 72/83 80/95 -10 -10 10 10
dB A A
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3.4
3.4.1
Electrical and Environmental Specifications
Operating Conditions, Absolute Maximum Ratings, and Power Requirements
The operating conditions are specified in Table 3-15. The absolute maximum ratings are listed in Table 3-16 for the CX81801, Table 3-17 for the CX20493, and Table 3-18 for the CX20442. The current and power requirements are listed in Error! Reference source not found.. Table 3-15. Operating Conditions
Parameter Supply Voltage Operating Ambient Temperature Symbol VDD T A Limits +3.0 to +3.6 0 to +70 Units VDC C
Table 3-16. CX81801 Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Storage Temperature Range Analog Inputs Voltage Applied to Outputs in High Impedance (Off) State DC Input Clamp Current DC Output Clamp Current Static Discharge Voltage (25C) Latch-up Current (25C) * VGG = +3.3V 0.3V, or +5V 0.25V Symbol VDD V IN T STG V IN V HZ I I V I IK Limits -0.5 to +4.0 -0.5 to + (VGG + 0.5)* -55 to +125 -0.3 to (VAA + 0.5) -0.5 to + (VGG + 0.5)* 20 20 2500 400 Units VDC VDC C VDC VDC mA mA VDC mA
OK
ESD
TRIG
Table 3-17. CX20493 Absolute Maximum Ratings
Parameter Regulator Supply Voltage Supply Voltage Pin Voltage Storage Temperature Range Voltage Applied to Outputs in High Impedance (Off) State Static Discharge Voltage (HBM) Latch-up Current (25C) Symbol PWR+ DVdd, AVdd I/O T STG V HZ V I ESD Limits -0.5 to +4.1 -0.5 to +3.6 -0.5 to DVdd + 0.5 -55 to +125 -0.5 to +5.5 2500 250 Units VDC VDC VDC C VDC V mA
TRIG
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CX81801-7x/8x SmartV.XX Modem Data Sheet Table 3-18. CX20442 Absolute Maximum Ratings
Parameter Analog Supply Voltage Digital Supply Voltage Storage Temperature Range Digital Inputs Analog Inputs DC Input Clamp Current DC Output Clamp Current Static Discharge Voltage (25 C) Latch-up Current (25 C) Notes: 1. Ratings specified for +3.3 V operation. 2. Voltages referenced to ground (VSS). Symbol AVDD VDD TSTG VIN VIN IIK IOK VESD ITRIG Limits -0.3 to +4.6 -0.3 to +4.6 -55 to +150 -0.3 to (VDD + 0.3) -0.3 to + (AVDD + 0.3) 10 10 2500 150 Units V V C V V mA mA V mA
Table 3-19. Current and Power Requirements
Mode Typical Current (Ityp) (mA) 62 60 18 1.5 Maximum Current (Imax) (mA) 71 69 21 2.0 Typical Power (Ptyp) (mW) 205 198 59 5 Maximum Power (Pmax) (mW) 256 248 76 7 Notes
CX81801 Modem and CX20493 LSD Normal Mode: Off-hook, normal data connection Normal Mode: On-hook, idle, waiting for ring Sleep Mode CX20442 VC (Optional) Normal Mode
f = 28.224 MHz f = 28.224 MHz f = 0 MHz
Notes: 1. Operating voltage: VDD = +3.3V 0.3V. 2. Test conditions: VDD = +3.3V for typical values; VDD = +3.6V for maximum values. 3. Input Ripple 0.1 Vpeak-peak. 4. f = Internal frequency. 5. Typical power (Ptyp) computed from Ityp: Ptyp = Ityp * 3.3V; Maximum power (Pmax) computed from Imax: Pmax = Imax * 3.6V.
Handling CMOS Devices
The device contains circuitry to protect the inputs against damage due to high static voltages. However, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltage. An unterminated input can acquire unpredictable voltages through coupling with stray capacitance and internal cross talk. Both power dissipation and device noise immunity degrades. Therefore, all inputs should be connected to an appropriate supply voltage. Input signals should never exceed the voltage range from -0.5V to + (VGG + 0.5V). This prevents forward biasing the input protection diodes and possibly entering a latch up mode due to high current transients.
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3.4.2
3.4.2.1
Interface and Timing Waveforms
External Memory Bus Timing
The external memory bus timing is listed in Table 3-20 and illustrated in Figure 3-9.
Table 3-20. Timing - External Memory Bus
Symbol t t t t t t t t t t t t FI CYC AS ES RW RDS RDH AS ES WW WTD Parameter Internal Operating Frequency Internal Operating Clock Cycle Read READ# High to Address Valid READ# High to ES Valid READ# Pulse Width Read Data Valid to READ# High READ# High to Read Data Hold Write WRITE# High to Address Valid WRITE# High to ES Valid WRITE# to WRITE# Pulse Width WRITE# Low to Write Data Valid WRITE# High to Write Data Hold - - 15 - 5.0 6.5 8 - 5 - 8 11 105 8.2 - ns ns ns ns ns - - 15 6.1 0 6.5 8 - - 0 9 11 105 - - ns ns ns ns ns Min 28.224 30 Typ. - - Max - - Units MHz ns
WTH Notes: 1. ES = RAMSEL# or ROMSEL#. 2. Read pulse width and write pulse width: RAM: t ,t = 0.5 t = 15 for Non-Extended Cycle Timing RW WW CYC ROM: t ,t = 3.5 t = 105 for Extended Cycle Timing RW WW CYC 3. Memory speed determination: RAM: tACCESS = t -t -t = 330 - 8 - 6.1 = 15.9 ns (i.e., use 15 ns memory) CYC ES RDS ROM: tACCESS = 4(t )-t -t = 4(30) - 8 - 6.1 = 105.9 ns (i.e., use 90 ns memory). CYC ES RDS 4. Output Enable to Output Delay Timing: RAM: t =t -t = 0.5(t )-t = 15 - 6.1 = 8.9 ns OE RW RDS CYC RDS ROM: t =t -t = 3.5(t )-t = 105 - 6.1 = 98.9 ns. OE RW RDS CYC RDS
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Figure 3-9. Waveforms - External Memory Bus
t C2* t A[18:0] t ES#** t READ# t D[7:0] * C2 = Internal Phase 2 clock. ** ES# = RAMSEL# or ROMSEL#. Read Timing RDS t RDH ES AS
CYC
RW
t C2*
CYC
t A[18:0] t ES#** t WRITE# t D[7:0] * C2 = Internal Phase 2 clock. ** ES# = RAMSEL# or ROMSEL#. WTD WW
AS
ES
t
WTH
Write Timing
100491 F3-09 WF EB
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3.4.2.2
Parallel Host Bus Timing
The parallel host bus timing is listed in Table 3-21 and illustrated in Figure 3-10.
Table 3-21. Timing - Parallel Host Bus
Symbol t t t t t t t Address Setup Address Hold Chip Select Setup Chip Select Hold HRD# Strobe Width Read Data Delay Read Data Hold Parameter Min READ (See Notes 1, 2, 3, 4, and 5) 5 10 0 10 45 - 5 WRITE (See Notes 1, 2, 3, 4, and 5) 5 15 0 10 75 - Max - - - - - 25 - Units ns ns ns ns ns ns ns
AS AH CS CH RD DD DRH
t t t t t t t
AS AH CS CH WT DS
Address Setup Address Hold Chip Select Setup Chip Select Hold HWT# Strobe Width
- - - - - 20
ns ns ns ns ns ns
Write Data Setup (see Note 4)
Write Data Hold (see Note 5) 5 - ns DWH Notes: 1. When the host executes consecutive Rx FIFO reads, a minimum delay of 2 times the internal CPU clock cycle plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of HRD# to the falling edge of the next Host Rx FIFO HRD# clock. 2. When the Host executes consecutive Tx FIFO writes, a minimum delay of 2 times the internal CPU clock cycle plus 15 ns (85.86 ns at 28.224 MHz) is required from the falling edge of HWT# to the falling edge of the next Host Tx FIFO HWT# clock. 3. t is measured from the point at which both HCS# and HWT# are active. DS 4. t is measured from the point at which either HCS# and HWT# become inactive. DWH 5. Clock frequency = 28.224 MHz clock.
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CX81801-7x/8x SmartV.XX Modem Data Sheet
Figure 3-10. Waveforms - Parallel Host Bus
HA[2-0] tAS HCS# tCS HRD# tRD HWT# tCH tAH
HD[7-0] tDD tDRH
a. Host Read
HA[2-0] tAS tAH
HCS# tCS HRD# tWT HWT# tDS HD[7-0] tDWH tCH
b. Host Write
100491 F3-10 WF-HB
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3.4.2.3
Serial DTE Interface
The serial DTE interface waveforms for 4800 and 9600 bps are illustrated in Figure 3-11.
Figure 3-11. Waveforms - Serial DTE Interface
TXCLK 4800 BPS TXD 4800 BPS TXCLK 9600 BPS
TXD 9600 BPS
NOTE: THIS FIGURE IS VALID FOR SYNCHRONOUS MODE ONLY. THERE IS NO RELATIONSHIP BETWEEN NOTE: TXD AND TXCLK IN ASYNCHRONOUS MODE.
a. Transmit
RXCLK 4800 BPS RXD 4800 BPS RXCLK 9600 BPS
RXD 9600 BPS
NOTE: THIS FIGURE IS VALID FOR SYNCHRONOUS MODE ONLY. THERE IS NO RELATIONSHIP BETWEEN NOTE: RXD AND RXCLK IN ASYNCHRONOUS MODE.
b. Receive
1227F3-14 WF-Ser DTE
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CX81801-7x/8x SmartV.XX Modem Data Sheet
3.5
Crystal Specifications
Crystal specifications are listed in Table 3-22. Table 3-22. Crystal Specifications
Characteristic Frequency Calibration Tolerance Frequency Stability vs. Temperature Frequency Stability vs. Aging Oscillation Mode Calibration Mode Load Capacitance, C L Shunt Capacitance, C O Series Resistance, R 1 Drive Level Operating Temperature Storage Temperature Value 28.224 MHz nominal 50 ppm at 25C (C = 16.5 and 19.5 pF) L 35 ppm (0C to 70C) 20 ppm/5 years Fundamental Parallel resonant 18 pF nom. 7 pF max. 35-60 max. @20 nW drive level 100W correlation; 500W max. 0C to 70C -40C to 85C
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CX81801-7x/8x SmartV.XX Modem Data Sheet
4.
Package Dimensions
The 128-pin TQFP package dimensions are shown in Figure 4-1. The 32-pin TQFP package dimensions are shown in Figure 4-2. The 28-pin QFN package dimensions are shown in Figure 4-3.
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CX81801-7x/8x SmartV.XX Modem Data Sheet
Figure 4-1. Package Dimensions - 128-Pin TQFP
E E1 E2
PIN 1 REF
D
D1 D2
D1
e
b
Dim. A A1 A2 D D1 D2 E E1 E2 L L1 e b c Coplanarity
Millimeters Max. Min. 1.6 MAX 0.15 0.05 1.4 REF 22.25 21.75 20.0 REF 18.5 REF 16.25 15.75 14.0 REF 12.5 REF 0.75 0.5 1.0 REF 0.50 BSC 0.17 0.27 0.17 0.11 0.08 MAX
Inches* Max. Min. 0.0630 MAX 0.0020 0.0059 0.0551 REF 0.8563 0.8760 0.7874 REF 0.7283 REF 0.6201 0.6398 0.5512 REF 0.4921 REF 0.0197 0.0295 0.0394 REF 0.0197 BSC 0.0067 0.0043 0.0106 0.0067
E1
DETAIL A
A
A2
0.0031 MAX
Ref: 128-PIN TQFP (GP00-D264)
c A1 L1 DETAIL A
L
* Metric values (millimeters) should be used for PCB layout. English values (inches) are converted from metric values and may include round-off errors.
PD-TQFP-128 (040395)
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Figure 4-2. Package Dimensions - 32-pin TQFP
D D1 D2
PIN 1 REF
D
D1 D2
D1
e
b
DETAIL A
Dim. A
Millimeters Max. Min. 1.6 MAX 0.15 0.05 1.4 REF 9.25 8.75 7.0 REF 5.6 REF 0.75 0.5 1.0 REF 0.80 BSC 0.30 0.40 0.19 0.13 0.10 MAX
Inches* Max. Min. 0.0630 MAX 0.0020 0.3445 0.0059 0.3642 0.0551 REF 0.2756 REF 0.2205 REF 0.0197 0.0295 0.0394 REF 0.0315 BSC 0.0118 0.0051 0.0157 0.0075
D1
A1 A2 D D1 D2 L L1 e b c Coplanarity
A
A2
0.004 MAX
Ref: 32-PIN TQFP (GP00-D262)
c A1 L1 DETAIL A
PD-TQFP-32 (040395)
L
* Metric values (millimeters) should be used for PCB layout. English values (inches) are converted from metric values and may include round-off errors.
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CX81801-7x/8x SmartV.XX Modem Data Sheet
Figure 4-3. Package Dimensions - 28-Pin QFN
D
NOTE 3 A D1 A2 A3 28 28 Pin 1 Identifier Pin 1 Identifier 1 2 3 E1 E 1 2 3 E2 A1 D2
L b NOTE 1
e
TOP VIEW
SEATING PLANE
BOTTOM VIEW
CC C L b NOTE 1 e A1 10
Dimensions (Millimeters) Symbol Nom. e 0.5 BSC 0.60 0.50 L 0.23 0.28 b 2.95 D2 3.10 2.95 3.10 E2 A 0.85 0.01 A1 0.00 0.65 A2 A3 0.15 0.20 4.90 5.00 D 4.65 4.75 D1 E 4.90 5.00 4.65 E1 4.75 Ref. GP00-D682-001 Min. Max.
0.75 0.35 3.25 3.25 1.00 0.05 0.80 0.25 5.10 4.85 5.10 4.85
SECTION "C-C"
SCALE: NONE TERMINAL TIP
NOTES: 1. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.20 AND 0.25mm FROM TERMINAL TIP. 2. PACKAGE WARPAGE MAX 0.05mm. 3. APPLIED FOR EXPOSED PAD AND TERMINALS. EXCLUDE EMBEDDING PART OF EXPOSED PAD FROM MEASURING.
PD_GP00-D682-001
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5.
Parallel Host Interface
The modem supports a 16550A interface in parallel interface versions. The 16550A interface can operate in FIFO mode or non-FIFO mode. Non-FIFO mode is the same as 16450 interface operation. FIFO mode unique operations are identified.
5.1
Overview
The parallel interface registers and the corresponding bit assignments are shown in Table 5-1. The modem emulates the 16450/16550A interface and includes both a 16-byte receiver data first-in first-out buffer (RX FIFO) and a 16-byte transmit data first-in first-out buffer (TX FIFO). When FIFO mode is selected in the FIFO Control Register (FCR0 = 1), both FIFOs are operative. Furthermore, when FIFO mode is selected, DMA operation of the FIFO can also be selected (FCR3 = 1). When FIFO mode is not selected, operation is restricted to 16450 interface operation. The received data is read by the host from the Receiver Buffer (RX Buffer). The RX Buffer corresponds to the Receiver Buffer Register in a 16550A device. In FIFO mode, the RX FIFO operates transparently behind the RX Buffer. Interface operation is described with reference to the RX Buffer in both FIFO and non-FIFO modes. The transmit data is loaded by the host into the Transmit Buffer (TX Buffer). The TX Buffer corresponds to the Transmit Holding Register in a 16550A device. In FIFO mode, the TX FIFO operates transparently behind the TX Buffer. Interface operation is described with reference to the TX Buffer in both FIFO and non-FIFO modes.
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Table 5-1. Parallel Interface Registers
Register No. 7 6 Register Name Scratch Register (SCR) Ring Modem Status Register (MSR) Data Carrier Indicator (RI) Detect (DCD) Line Status Register (LSR) RX FIFO Error Data Set Ready (DSR) 7 6 5 4 Clear to Send (CTS) Bit No. 3 2 1 0 Scratch Register Delta Data Trailing Delta Data Delta Clear to Send Carrier Edge of Ring Set Ready (DCTS) (DDSR) Detect Indicator (DDCD) (TERI) Framing Error (FE) Parity Error (PE) Overrun Error (OE) Receiver Data Ready (DR)
5
Break Transmitter Transmitter Interrupt (BI) Buffer Empty (TEMT) Register Empty (THRE) 0 0 Local Loopback
4
Modem Control Register (MCR)
0
Out 2
Out 1
Request to Send (RTS)
Data Terminal Ready (DTR)
3
Line Control Register (LCR)
Divisor Latch Set Break Access Bit (DLAB) FIFOs Enabled Receiver Trigger MSB 0 FIFOs Enabled Receiver Trigger LSB 0
Stick Parity Even Parity Select (EPS) 0 0
Parity Enable (PEN)
Number of Word Length Word Length Stop Bits Select Bit 1 Select Bit 0 (STB) (WLS1) (WLS0) "0" if Interrupt Pending FIFO Enable
2
Interrupt Identify Register (IIR) (Read Only) FIFO Control Register (FCR) (Write Only)
Pending Pending Pending Interrupt ID Interrupt ID Interrupt ID Bit 2 Bit 1 Bit 0 DMA Mode Select Enable Modem Status Interrupt (EDSSI) TX FIFO Reset RX FIFO Reset
2
Reserved
Reserved
1 Interrupt Enable Register (IER) (DLAB = 0)
0
0
Enable Enable Receiver Transmitter Line Status Holding Interrupt Register (ELSI) Empty Interrupt (ETBEI)
Enable Received Data Available Interrupt (ERBFI)
0 Transmitter Buffer Register (DLAB = 0) (THR) 0 Receiver Buffer Register (RBR) (DLAB = 0) 1 Divisor Latch MSB Register (DLAB = 1) (DLM) 0 Divisor Latch LSB Register (DLAB = 1) (DLL)
Transmitter FIFO Buffer Register (Write Only) Receiver FIFO Buffer Register (Read Only) Divisor Latch MSB Divisor Latch LSB
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5.2
5.2.1
Register Signal Definitions
IER - Interrupt Enable Register (Addr = 1, DLAB = 0)
The IER enables five types of interrupts that can separately assert the HINT output signal (Table 5-2). A selected interrupt can be enabled by setting the corresponding enable bit to a 1, or disabled by setting the corresponding enable bit to a 0. Disabling an interrupt in the IER prohibits setting the corresponding indication in the IIR and assertion of HINT. Disabling all interrupts (resetting IER0 - IER3 to a 0) inhibits setting of any Interrupt Identifier Register (IIR) bits and inhibits assertion of the HINT output. All other system functions operate normally, including the setting of the Line Status Register (LSR) and the Modem Status Register (MSR). Bits 7-4 Not used.
Always 0. Bit 3 Enable Modem Status Interrupt (EDSSI).
This bit, when a 1, enables assertion of the HINT output whenever the Delta CTS (MSR0), Delta DSR (MSR1), Delta TER (MSR2), or Delta DCD (MSR3) bit in the Modem Status Register (MSR) is a 1. This bit, when a 0, disables assertion of HINT due to setting of any of these four MSR bits. Bit 2 Enable Receiver Line Status Interrupt (ELSI).
This bit, when a 1, enables assertion of the HINT output whenever the Overrun Error (LSR1), Parity Error (LSR2), Framing Error (LSR3), or Break Interrupt (LSR4) receiver status bit in the Line Status Register (LSR) changes state. This bit, when a 0, disables assertion of HINT due to change of the receiver LSR bits 1-4. Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETBEI).
This bit, when a 1, enables assertion of the HINT output when the Transmitter Empty bit in the Line Status Register (LSR5) is a 1. This bit, when a 0, disables assertion of HINT due to LSR5. Bit 0 Enable Receiver Data Available Interrupt (ERBFI) and Character Timeout in FIFO Mode.
This bit, when a 1, enables assertion of the HINT output when the Receiver Data Ready bit in the Line Status Register (LSR0) is a1 or character timeout occurs in the FIFO mode. This bit, when a 0, disables assertion of HINT due to the LSR0 or character timeout.
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5.2.2
FCR - FIFO Control Register (Addr = 2, Write Only)
The FCR is a write-only register used to enable FIFO mode, clear the RX FIFO and TX FIFO, enable DMA mode, and set the RX FIFO trigger level. Bits 7-6 RX FIFO Trigger Level.
FCR7 and FCR6 set the trigger level for the RX FIFO (Receiver Data Available) interrupt.
FCR7 0 0 1 1 FCR6 0 1 0 1 RX FIFO Trigger Level (Bytes) 01 04 08 14
Bits 5-4 Bit 3
Not used. DMA Mode Select.
When FIFO mode is selected (FCR0 = 1), FCR3 selects non-DMA operation (FCR3 = 0) or DMA operation (FCR3 = 1). When FIFO mode is not selected (FCR0 = 0), this bit is not used (the modem operates in non-DMA mode in 16450 operation).
DMA operation in FIFO mode.
RXRDY will be asserted when the number of characters in the RX FIFO is equal to or greater than the value in the RX FIFO Trigger Level (IIR0-IIR3 = 4h) or the received character timeout (IIR0-IIR3 = Ch) has occurred. RXRDY will go inactive when there are no more characters in the RX FIFO. TXRDY will be asserted when there are one or more empty (unfilled) locations in the TX FIFO. TXRDY will go inactive when the TX FIFO is completely full.
Non-DMA operation in FIFO mode.
RXRDY will be asserted when there are one or more characters in the RX FIFO. RXRDY will go inactive when there are no more characters in the RX FIFO. TXRDY will be asserted when there are no characters in the TX FIFO. TXRDY will go inactive when the first character is loaded into the TX FIFO Buffer. Bit 2 TX FIFO Reset.
When FCR2 is a 1, all bytes in the TX FIFO are cleared. This bit is cleared automatically by the modem. Bit 1 RX FIFO Reset.
When FCR1 is a 1, all bytes in the RX FIFO are cleared. This bit is cleared automatically by the modem. Bit 0 FIFO Enable.
When FCR0 is a 0, 16450 mode is selected and all bits are cleared in both FIFOs. When FCR0 is a 1, FIFO mode (16550A mode) is selected and both FIFOs are enabled. FCR0 must be a 1 when other bits in the FCR are written or they will not be acted upon.
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5.2.3
IIR - Interrupt Identifier Register (Addr = 2)
The Interrupt Identifier Register (IIR) identifies the existence and type of up to five prioritized pending interrupts. Four priority levels are set to assist interrupt processing in the host. The four levels, in order of decreasing priority, are: Highest: Receiver Line Status, 2: Receiver Data Available or Receiver Character Timeout, 3: TX Buffer Empty, and 4: Modem Status. When the IIR is accessed, the modem freezes all interrupts and indicates the highest priority interrupt pending to the host. Any change occurring in interrupt conditions are not indicated until this access is complete. Bits 7-6 FIFO Mode.
These two bits copy FCR0. Bits 5-4 Not Used.
Always 0. Bits 3-1 Highest Priority Pending Interrupt.
These three bits identify the highest priority pending interrupt (Table 5-2). Bit 3 is applicable only when FIFO mode is selected, otherwise bit 3 is a 0. Bit 0 Interrupt Pending.
When this bit is a 0, an interrupt is pending; IIR bits 1-3 can be used to determine the source of the interrupt. When this bit is a1, an interrupt is not pending.
Table 5-2. Interrupt Sources and Reset Control
Bit 31 0 0 Interrupt Identification Register Bit 2 Bit 1 Bit 0 Priority Level 0 1 0 1 1 0 -- Highest Interrupt Type None Receiver Line Status None Overrun Error OE (LSR1), Parity Error (PE) (LSR2), Framing Error (FE) (LSR3), or Break Interrupt (BI) (LSR4) Received Data Available (LSR0) or RX FIFO Trigger Level (FCR61 FCR7) Reached The RX FIFO contains at least 1 character and no characters have been removed from or input to the RX FIFO during the last 4 character times. TX Buffer Empty Delta CTS (DCTS) (MSR0), Delta DSR (DDSR) (MSR1), Trailing Edge Ring Indicator (TERI) (MSR3), or Delta DCD (DCD) (MSR4) Interrupt Set and Reset Functions Interrupt Source Interrupt Reset Control -- Reading the LSR
0
1
0
0
2
Received Data Available Character Time-out 1 Indication
Reading the RX Buffer or the RX FIFO drops below the Trigger Level Reading the RX Buffer
1
1
0
0
2
0 0
0 0
1 0
0 0
3 4
TX Buffer Empty Modem Status
Reading the IIR or writing to the TX Buffer Reading the MSR
Notes: 1. FIFO Mode only.
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5.2.4
LCR - Line Control Register (Addr = 3)
The Line Control Register (LCR) specifies the format of the asynchronous data communications exchange. Bit 7 Divisor Latch Access Bit (DLAB).
This bit must be set to a 1 to access the Divisor latch registers during a read or write operation. It must be reset to a 0 to access the Receiver Buffer, the Transmitter Buffer, or the Interrupt Enable Register. Bit 6 Set Break.
When bit 6 is a 1, the transmit data is forced to the break condition, i.e., space (0) is sent. When bit 6 is a 0, break is not sent. The Set Break bit acts only on the transmit data and has no effect on the serial in logic. Bit 5 Stick Parity.
When parity is enabled (LCR3 = 1) and stick parity is selected (LCR5 = 1), the parity bit is transmitted and checked by the receiver as a 0 if even parity is selected (LCR4 = 1) or as a 1 if odd parity is selected (LCR4 = 0). When stick parity is not selected (LCR3 = 0), parity is transmit and checked as determined by the LCR3 and LCR4 bits. Bit 4 Even Parity Select (EPS).
When parity is enabled (LCR3 = 1) and stick parity is not selected (LCR5 = 0), the number of 1s transmitted or checked by the receiver in the data word bits and parity bit is either even (LCR4 = 1) or odd (LCR4 = 0). Bit 3 Enable Parity (PEN).
When bit 3 is a 1, a parity bit is generated in the serial out (transmit) data stream and checked in the serial in (receive) data stream as determined by the LCR 4 and LCR5 bits. The parity bit is located between the last data bit and the first stop bit. Bit 2 Number of Stop Bits (STB).
This bit specifies the number of stop bits in each serial out character. If bit 2 is a 0, one stop bit is generated regardless of word length. If bit 2 is a 1 and 5-bit word length is selected, one and one-half stop bits are generated. If bit 2 is a 1 and a 6-, 7-, or 8-bit word length is selected, two stop bits are generated. The serial in logic checks the first stop bit only, regardless of the number of stop bits selected. Bits 1-0 Word Length Select (WLS0 and WLS1).
These two bits specify the number of bits in each serial in or serial out character. The encoding of bits 0 and 1 is:
Bit 1 0 0 1 1 Bit 0 0 1 0 1 Word Length 5 Bits (Not supported) 6 Bits (Not supported) 7 Bits 8 Bits
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5.2.5
MCR - Modem Control Register (Addr = 4)
The Modem Control Register (MCR) controls the interface with the modem or data set. Bit 7-5 Not used.
Always 0. Bit 4 Local Loopback.
When this bit is set to a 1, the diagnostic mode is selected and the following occurs: Data written to the Transmit Buffer is looped back to the Receiver Buffer. The DTS (MCR0), RTS (MCR1), Out1 (MCR2), and Out2 (MCR3) modem control register bits are internally connected to the DSR (MSR5), CTS (MSR4), RI (MSR6), and DCD (MSR7) modem status register bits, respectively. Bit 3 Output 2.
When this bit is a 1, HINT is enabled. When this bit is a 0, HINT is in the high impedance state. Bit 2 Output 1.
This bit is used in local loopback (see MCR4). Bit 1 Request to Send (RTS).
This bit controls the Request to Send (RTS) function. When this bit is a 1, RTS is on. When this bit is a 0, RTS is off. Bit 0 Data Terminal Ready (DTR).
This bit controls the Data Terminal Ready (DTR) function. When this bit is a 1, DTR is on. When this bit is a 0, DTR is off.
5.2.6
LSR - Line Status Register (Addr = 5)
This 8-bit register provides status information to the host concerning data transfer. Bit 7 RX FIFO Error.
In the 16450 mode, this bit is not used and is always 0. In the FIFO mode, this bit is set if there are one or more characters in the RX FIFO with a parity error, framing error, or break indication detected. This bit is reset to a 0 when the host reads the LSR and none of the above conditions exist in the RX FIFO. Bit 6 Transmitter Empty (TEMT).
This bit is set to a 1 whenever the TX Buffer (THR) and equivalent of the Transmitter Shift Register (TSR) are both empty. It is reset to a 0 whenever either the THR or the equivalent of the TSR contains a character. In the FIFO mode, this bit is set to a 1 when ever the TX FIFO and the equivalent of the TSR are both empty.
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CX81801-7x/8x SmartV.XX Modem Data Sheet
Bit 5
Transmitter Holding Register Empty (THRE) [TX Buffer Empty].
This bit, when set, indicates that the TX Buffer is empty and the modem can accept a new character for transmission. In addition, this bit causes the modem to issue an interrupt to the host when the Transmit Holding Register Empty Interrupt Enable bit (IIR1) is set to 1. The THRE bit is set to a 1 when a character is transferred from the TX Buffer. The bit is reset to 0 when a byte is written into the TX Buffer by the host. In the FIFO mode, this bit is set when the TX FIFO is empty; it is cleared when at least one byte is in the TX FIFO. Bit 4 Break Interrupt (BI).
This bit is set to a 1 whenever the received data input is a space (logic 0) for longer than two full word lengths plus 3 bits. The BI bit is reset when the host reads the LSR. Bit 3 Framing Error (FE).
This bit indicates that the received character did not have a valid stop bit. The FE bit is set to a 1 whenever the stop bit following the last data bit or parity bit is detected as a logic o (space). The FE bit is reset to a 0 when the host reads the LSR. In the FIFO mode, the error indication is associated with the particular character in the FIFO it applies to; the FE bit is set to a 1 when this character is loaded into the RX Buffer. Bit 2 Parity Error (PE).
This bit indicates that the received data character in the RX Buffer does not have the correct even or odd parity, as selected by the Even Parity Select bit (LCR4) and the Stick Parity bit (LCR5). The PE bit is reset to a 0 when the host reads the LSR. In the FIFO mode, the error indication is associated with the particular character in the it applies to; the PE bit is set to a 1 when this character is loaded into the RX Buffer. Bit 1 Overrun Error (OE).
This bit is set to a 1 whenever received data is loaded into the RX Buffer before the host has read the previous data from the RX Buffer. The OE bit is reset to a 0 when the host reads the LSR. In the FIFO mode, if data continues to fill beyond the trigger level, an overrun condition will occur only if the RX FIFO is full and the next character has been completely received. Bit 0 Receiver Data Ready (DR).
This bit is set to a 1 whenever a complete incoming character has been received and has been transferred into the RX Buffer. The DR bit is reset to a 0 when the host reads the RX Buffer. In the FIFO mode, the DR bit is set when the number of received data bytes in the RX FIFO equals or exceeds the trigger level specified in FCR0-FCR1.
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5.2.7
MSR - Modem Status Register (Addr = 6)
The Modem Status Register (MSR) reports current state and change information of the modem. Bits 4-7 supply current state and bits 0-3 supply change information. The change bits are set to a 1 whenever a control input from the modem changes state from the last MSR read by the host. Bits 0-3 are reset to 0 when the host reads the MSR or upon reset. Whenever bits 0, 1, 2, or 3 are set to a 1, a Modem Status Interrupt (IIR0-IIR3 = 0) is generated. Bit 7 Data Carrier Detect (DCD).
This bit indicates the logic state of the DCD# (RLSD#) output. If Loopback is selected (MCR4 = 1), this bit reflects the state of the Out2 bit in the MCR (MCR3). Bit 6 Ring Indicator (RI).
This bit indicates the logic state of the RI# output. If Loopback is selected (MCR4 = 1), this bit reflects the state of the Out1 bit in the MCR (MCR2). Bit 5 Data Set Ready (DSR).
This bit indicates the logic state of the DSR# output. If Loopback is selected (MCR4 = 1), this bit reflects the state of the DTR bit in the MCR (MCR0). Bit 4 Clear to Send (CTS).
This bit indicates the logic state of the CTS# output. If Loopback is selected (MCR4 = 1), this bit reflects the state of the RTS bit in the MCR (MCR1). Bit 3 Delta Data Carrier Detect (DDCD).
This bit is set to a 1 when the DCD bit changes state since the MSR was last read by the host. Bit 2 Trailing Edge of Ring Indicator (TERI).
This bit is set to a 1 when the RI bit changes from a 1 to a 0 state since the MSR was last read by the host. Bit 1 Delta Data Set Ready (DDSR).
This bit is set to a 1 when the DSR bit has changed since the MSR was last read by the host. Bit 0 Delta Clear to Send (DCTS).
This bit is set to a 1 when the CTS bit has changed since the MSR was last read by the host.
5.2.8
RBR - RX Buffer (Receiver Buffer Register) (Addr = 0, DLAB = 0)
The RX Buffer (RBR) is a read-only register at location 0 (with DLAB = 0). Bit 0 is the least significant bit of the data, and is the first bit received.
5.2.9
THR - TX Buffer (Transmitter Holding Register) (Addr = 0, DLAB = 0)
The TX Buffer (THR) is a write-only register at address 0 when DLAB = 0. Bit 0 is the least significant bit and the first bit sent.
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CX81801-7x/8x SmartV.XX Modem Data Sheet
5.2.10
Divisor Registers (Addr = 0 and 1, DLAB = 1)
The Divisor Latch LS (least significant byte) and Divisor Latch MS (most significant byte) are two read-write registers at locations 0 and 1 when DLAB = 1, respectively. The baud rate is selected by loading each divisor latch with the appropriate hex value. Programmable values corresponding to the desired baud rate are listed in Table 5-3. 1. SCR - Scratch Register (Addr = 7)
The Scratchpad Register is a read-write register at location 7. This register is not used by the modem and can be used by the host for temporary storage. Table 5-3. Programmable Baud Rates
Divisor Latch (Hex) MS LS 06 00 04 17 03 00 01 80 00 C0 00 60 00 30 00 18 00 0C 00 06 00 04 00 03 00 02 00 01 00 00 Divisor (Decimal) 1536 1047 768 384 192 96 48 24 12 6 4 3 2 1 NA Baud Rate 75 110 150 300 600 1200 2400 4800 9600 19200 28800 38400 57600 115200 230400
5.3
5.3.1
Receiver FIFO Interrupt Operation
Receiver Data Available Interrupt
When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (RX Data Available) is enabled (IER0 = 1), receiver interrupt operation is as follows: The Receiver Data Available Flag (LSR0) is set as soon as a received data character is available in the RX FIFO. LSR0 is cleared when the RX FIFO is empty. The Receiver Data Available interrupt code (IIR0-IIR4 = 4h) is set whenever the number of received data bytes in the RX FIFO reaches the trigger level specified by FCR6-FCR7 bits; it is cleared whenever the number of received data bytes in the RX FIFO drops below the trigger level specified by FCR6-FCR7 bits. The HINT interrupt is asserted whenever the number of received data bytes in the RX FIFO reaches the trigger level specified by FCR6-FCR7 bits. HINT interrupt is deasserted when the number of received data bytes in the RX FIFO drops below the trigger level specified by FCR6-FCR7 bits.
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CX81801-7x/8x SmartV.XX Modem Data Sheet
5.3.2
Receiver Character Timeout Interrupts
When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (Receiver Data Available) is enabled (IER0 = 1), receiver character timeout interrupt operation is as follows: 1. A Receiver character timeout interrupt code (IIR0-IIR3 = Ch) is set if at least one received character is in the RX FIFO, the most recent received serial character was longer than four continuous character times ago (if 2 stop bits are specified, the second stop bit is included in this time period), and the most recent host read of the RX FIFO was longer than four continuous character times ago.
5.4
5.4.1
Transmitter FIFO Interrupt Operation
Transmitter Empty Interrupt
When the FIFO mode is enabled (FCR0 = 1) and transmitter interrupt (TX Buffer Empty) is enabled (IER0 = 1), transmitter interrupt operation is as follows: The TX Buffer Empty interrupt code (IIR0-IIR3 = 2h) will occur when the TX Buffer is empty; it is cleared when the TX Buffer is written to (1 to 16 characters) or the IIR is read. The TX Buffer Empty indications will be delayed 1 character time minus the last stop bit time whenever the following occur: THRE = 1 and there have not been at least two bytes at the same time in the TX FIFO Buffer since the last setting of THRE was set. The first transmitter interrupt after setting FCR0 will be immediate.
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NOTES
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